Elementary Mr. Watson: Running the Signal Gauntlet
The Shaughnessy Report: Winning the Signal Integrity Battle
Connect the Dots: How to Avoid Five Common Causes of Board Failure
DesignCon Presents 2020 Conference Programming
November 5, 2019 | DesignConEstimated reading time: 4 minutes
DesignCon, the nation’s largest event for chip, board, and systems design engineers, today announced its 2020 conference schedule presenting 14 newly refined and reorganized tracks covering a broad range of highly technical sessions, boot camps, tutorials, and more to fit the needs of the hardware design engineering community. Hot topics of interest for this year’s programming include signal integrity (SI) and power integrity (PI) for single-multi die, interposer and packaging, modeling and analysis of interconnects, featured within a breadth of sessions. DesignCon returns to Silicon Valley for its 25th year, taking place January 28-30 at the Santa Clara Convention Center.
The DesignCon premier educational conference is curated by the Technical Program Committee (TPC), an expert panel of more than 90 industry professionals who review and update the curriculum each year to meet the needs of the ever-evolving high-speed communications and semiconductors industry for 25 years running. With more than 100 technical paper sessions, panels, and tutorials spanning 14 tracks, DesignCon’s three-day conference program covers all aspects of hardware design, including high-speed serial design, machine learning, and much more. For more in-depth information on each track, please visit here.
DesignCon 2020 will additionally welcome a number of leading industry experts as panel and session speakers, including recently elected I/O Buffer Information Specification (IBIS) Open Forum chair, Randy Wolff. As chair, Mr. Wolff provides leadership for this influential discipline and is a valued partner of DesignCon.
“DesignCon provides unrivaled access to today’s leading experts who are advancing high speed communications, technology and design across a variety of applications,” Wolff said. “To continue solving problems and enabling new technologies, a broad community of skilled engineers need to come together to share a breadth of knowledge and information—DesignCon is the ideal forum for this exchange, and IBIS is proud to be a partner and to support the continued innovation within this industry.”
Featured conference content of interest at DesignCon 2020 include:
Under the Hood: Understand the Software that Drives Electromagnetic Simulation Tools (Boot Camp)
In this full-day boot camp, presented by SI experts, David Correia and Raul Stavoli from Carlisle IT, attendees will learn different numerical techniques ranging from computational electromagnetics to frequency and time-domain conversions. See how S-parameters are created in a full-wave solver, how they can be converted between time and frequency domains, and what type of information is relevant in each domain. Also focused on is how to start with a simple finite-difference time-domain solver, followed by a finite-element solver in frequency domain to show the advantages and disadvantages of each method. Finally, the boot camp will address the information contained in an S-parameter file, and how to extract relevant content in both frequency and time-domains.
Open-Source Software Tools for Signal Integrity (Tutorial)
This session will introduce engineers to a Python-based open-source software tool called Signal Integrity released last year on the Python Packaging Index. This software is ideal for calculating single-ended or mixed-mode s-parameters of interconnected networks, frequency and time-domain de-embedding, and linear simulation of systems. Peter Pupalaikis, vice president, Advanced Technology Development, Teledyne LeCroy will walk-through several use-cases, teaching how to use the tool to solve various problems, along with providing other educational content on s-parameters.
Automatic Channel Condition Detection & Tuning Using Machine Learning Surrogate Models for 56G PAM4 Channels (Technical Session)
Machine-learning expert Chris Cheng presents the follow up to their previous paper on accelerating channel optimization using principal component analysis. In this session, Cheng will create families of surrogate models in the reduced dimension PCA space based on various channel conditions. When a new system topology is encountered, random points within the PCA space is sampled. The resulting performance is compared against the families of surrogate models and the closest solution is considered the nearest channel condition model. The optimal operating can then be easily set based on precomputed optimal setting for that surrogate model. Alternatively, the precompute settings can be used as seed values for circuit level auto tuning.
Component Design Specification Study for Electrical Serial Links Beyond 112G (Technical Session)
Based on compatibility and scalability requirements, electrical solutions for beyond 112Gbps need to be evaluated in PCB-based, orthogonal and cable-based backplane configurations. However, the design goals of the key components for beyond 112G are unclear. This paper serves as a trailblazer to explore the key component requirements. A top-down method is introduced for decomposing end-to-end link performance requirements from Salz-SNR analysis under PAM-based modulation schemes, down to the performance requirements for each individual component, such as connector, cable and PCB. Two sets of component design guidelines for 224G copper transmissions are proposed for smaller chassis/boxes and large chassis as examples. A series of highly esteemed Industry experts from Xilinx, ZTE, and more will guide attendees throughout this technical session.
Optimized Wireless System Design with Minimal RFI Using Antenna Near Field Approach (Technical Session)
From the Amazon Lab 126 team, RF interference is one of the major problems in modern day consumer electronics. This deep dive of their paper presents a workflow that provides a new perspective on RFI mitigation by observing the antenna’s near field as opposed to manipulating the noise source. By making changes to antenna structure and its near field characteristics considerable RFI improvement can be achieved.
DesignCon 2020 is also supported by The Institute of Electrical and Electronics Engineers (IEEE), offering its accreditation to conference attendees. Each conference hour is equivalent to one professional development hour (PDH), and 10 PDH’s result in one continuing education unit (CEU) and an official IEEE certificate. IEEE accreditation can be used to meet training requirements, stand out to future employers, and maintain an engineering license.
Share on:
Testimonial
"In a year when every marketing dollar mattered, I chose to keep I-Connect007 in our 2025 plan. Their commitment to high-quality, insightful content aligns with Koh Young’s values and helps readers navigate a changing industry. "
Brent Fischthal - Koh YoungSuggested Items
Trouble in Your Tank: Implementing Direct Metallization in Advanced Substrate Packaging
09/15/2025 | Michael Carano -- Column: Trouble in Your TankDirect metallization systems based on conductive graphite are gaining popularity throughout the world. The environmental and productivity gains achievable with this process are outstanding. Direct metallization reduces the costs of compliance, waste treatment, and legal issues related to chemical exposure. A graphite-based direct plate system has been devised to address these needs.
Closing the Loop on PCB Etching Waste
09/09/2025 | Shawn Stone, IECAs the PCB industry continues its push toward greener, more cost-efficient operations, Sigma Engineering’s Mecer System offers a comprehensive solution to two of the industry’s most persistent pain points: etchant consumption and rinse water waste. Designed as a modular, fully automated platform, the Mecer System regenerates spent copper etchants—both alkaline and acidic—and simultaneously recycles rinse water, transforming a traditionally linear chemical process into a closed-loop system.
Driving Innovation: Depth Routing Processes—Achieving Unparalleled Precision in Complex PCBs
09/08/2025 | Kurt Palmer -- Column: Driving InnovationIn PCB manufacturing, the demand for increasingly complex and miniaturized designs continually pushes the boundaries of traditional fabrication methods, including depth routing. Success in these applications demands not only on robust machinery but also sophisticated control functions. PCB manufacturers rely on advanced machine features and process methodologies to meet their precise depth routing goals. Here, I’ll explore some crucial functions that empower manufacturers to master complex depth routing challenges.
Trouble in Your Tank: Minimizing Small-via Defects for High-reliability PCBs
08/27/2025 | Michael Carano -- Column: Trouble in Your TankTo quote the comedian Stephen Wright, “If at first you don’t succeed, then skydiving is not for you.” That can be the battle cry when you find that only small-diameter vias are exhibiting voids. Why are small holes more prone to voids than larger vias when processed through electroless copper? There are several reasons.
The Government Circuit: Navigating New Trade Headwinds and New Partnerships
08/25/2025 | Chris Mitchell -- Column: The Government CircuitAs global trade winds continue to howl, the electronics manufacturing industry finds itself at a critical juncture. After months of warnings, the U.S. Government has implemented a broad array of tariff increases, with fresh duties hitting copper-based products, semiconductors, and imports from many nations. On the positive side, tentative trade agreements with Europe, China, Japan, and other nations are providing at least some clarity and counterbalance.