Book Excerpt: Power Integrity by Example

Estimated reading time: 2 minutes

The following is an excerpt from The Printed Circuit Designer's Guide to... Power Integrity by Example, written by Fadi Deek of Mentor, a Siemens Business. In this free eBook, Deek addresses problematic issues within electronic transmissions, and presents a variety of simulations and analyses in every chapter.

In our first book, The Printed Circuit Designer's Guide to... Signal Integrity by Example, we discussed some of the important signal integrity issues that a signal might face as it propagates from transmitter to receiver. In this sequel, we discuss the power integrity of the power distribution network, or PDN. One of the main requirements of a PDN, as defined by the IEEE EMC symposium, is to provide a low-impedance reference path to signals. A high impedance of a PDN yields inadequate current delivery to the receiver. Thus, this can be a root cause for signal integrity issues, such as:

• Voltage ripples
• Jitter/timing violations and false switching
• Bit errors
• Noise propagation throughout the board

In reality, a PDN is the path or interconnect from the voltage regulator model, or VRM (source of power supply), to the integrated circuits, or ICs (active devices), that consists of boards and packages with planes, routed traces, and decoupling capacitors. The scope of this book focuses on controlling the impedance of the PDN at the PCB level.

Though there are a few general design guidelines that will help to achieve a low impedance, those guidelines can rarely be followed in their entirety. This is why it’s so important to understand how the components of a PDN affect the impedance profile.

This book starts with an analysis of one of the main components of the PDN—the cavity. The impedance profile of the cavity is examined in the frequency domain in the form of Z-parameters. Series and parallel resonance occurrences are discussed and formulas are given to calculate their location.

Next, elements of the cavity, such as the VRM decoupling capacitors and stitching vias, are added one at a time to understand their influence on the impedance of the cavity. An important conclusion is made about how to make the cavity as transparent as possible for signals’ return paths. This step-by-step explanation provides the engineer with a firm understanding of what to expect when adding any of those elements. Having such a priori knowledge helps to efficiently design the PDN.

The final two chapters discuss the heavily-overlooked issue of coupling between signal vias passing through the cavity. At the high data rates of today’s designs, it is very easy to excite high-frequency resonant modes that are intrinsic to the geometry of a cavity. A signal loses energy to such high-frequency modes and can fall victim to coupling to them. Equipped with an understanding of this phenomenon, methods for suppressing such noise are provided.

In addition to this book, a detailed explanation of power integrity analysis can be found in the book Principles of Power Integrity for PDN Design— Simplified: Robust and Cost Effective Design for High Speed Digital Products by Eric Bogatin and Larry Smith published by Prentice Hall in 2017.

To download your free copy of The Printed Circuit Designer’s Guide to…Power Integrity by Example, click here.

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