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Financial Risks of Ignoring Copper Grain
November 1, 2023 | Alex Stepinski, Stepinski GroupEstimated reading time: 1 minute

The topic of intrinsic copper structure has been largely neglected in discussions regarding the PCB fabrication quality control process. At face value, this seems especially strange considering that copper has been the primary conductor in all wiring boards and substrates since they were first invented. IPC and other standards almost exclusively address copper thickness with some mild attention being paid to surface structure for signal loss-mitigation/coarse properties.
Yet we still lack standards references as to what the actual copper grain structure should look like to optimize microvia reliability, what a target pad and capture-annulus should look like after laser drilling and post-treatment, and what copper grain structure yields which etch rate for optimizing the substrate differential etch and resolution limit. These topics generally fall into the category of individual factory know-how.
In this article, we will present examples of applications where improved measurement and control of copper grain structure and topography provide significant gains in value to the PCB fab process.
In the case of microvias, in addition to the traditional chemical analyses, white-light microscopy inspections, weight gains/losses, and SIR readings associated with laser drill and the metallization of microvias, best practice has recently found that three different inspection steps for copper structural assessment to assure high-reliability results are also valuable to de-risking the process.
To read the rest of this article, which appeared in the October 2023 issue of PCB Magazine, click here.
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EIPC 2025 Winter Conference, Day 2: A Roadmap to Material Selection
02/20/2025 | Pete Starkey, I-Connect007The EIPC 2025 Winter Conference, Feb. 4-5, in Luxembourg City, featured keynotes and two days of conference proceedings. The keynote session and first-day conference proceedings are reported separately. Here is my review of the second day’s conference proceedings. Delegates dutifully assembled bright and early, well-rested and eager to participate in the second day’s proceedings of the EIPC Winter Conference in Luxembourg.
Designers Notebook: Addressing Future Challenges for Designers
02/06/2025 | Vern Solberg -- Column: Designer's NotebookThe printed circuit board is and will probably continue to be the base platform for most electronics. With the proliferation of new generations of high I/O, fine-pitch surface mount semiconductor package variations, circuit interconnect is an insignificant factor. Circuit board designers continually face challenges such as component quantity and complexity, limited surface area, and meeting the circuit board’s cost target. The printed circuit design engineer’s prominent position demands the development of efficiently manufacturable products that perform without compromise.
DesignCon 2025, Day 2: It’s All About AI
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