Elementary Mr. Watson: Ensuring a Smooth Handoff From PCB Design to Fabrication
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Connect the Dots: Designing for Reality—Routing, Final Fab, and QC
BOOK EXCERPT: 'The Printed Circuit Designer’s Guide to... Stackups—The Design within the Design', Chapter 5
January 30, 2024 | I-Connect007 Editorial TeamEstimated reading time: 1 minute
This excerpt is from The Printed Circuit Designer’s Guide to... Stackups—The Design within the Design, Chapter 5 by Bill Hargin, Z-Zero
Chapter 5: Impedance Planning
In my work, I deal with impedance and the entire ecosystem surrounding it daily. Whenever I talk to hardware teams, they often ask “how can two fabricators come back with two totally different designs for the same target impedance?” An example can help answer this question.
A client provided a stackup design which I ran through Z-planner Enterprise software. I compared these results with results from the HyperLynx field solver and the values in the stackups, which are often from unknown tools or with a few details obscured. Figure 5.1 shows a few examples from the same design.
The two stackup environments—Z-planner Enterprise and HyperLynx—showed up to 6-ohm differences for single-ended signals and up to 13 ohms for differential signals, compared to fabricator values. All of the signal-integrity simulations in the world cannot help if we assume a target impedance but the actual fabricated design is off this much. Electronic design automation (EDA) tools such as these can be super useful if you know what they are really modeling. Even here, the results are only as good as the data put in.
Factors That Impact Impedance
The primary parameters that affect impedance are shown in Table 5.1, including their relative contributions.
If you work this list top to bottom, you will be better equipped to dial in your nominal parameters with enough margin. Yet, I regularly see engineering teams straining to perform complex analyses using datasets with questionable merit, and without fully grasping these parameters and priorities. For example, I have never seen detailed, per-layer, percent-copper values from actual PCB layouts being used by PCB fabricators to compute pressed prepreg thicknesses.
Number 4 in Table 5.1 can be particularly problematic. For increased accuracy, keep track of not only the material family, but also resin content (%), and frequency.
Number 5, trace width, is closely tied to fabricator etching processes.
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