Estimated reading time: 6 minutes

Designers Notebook: Addressing Future Challenges for Designers

The printed circuit board is and will probably continue to be the base platform for most electronics. With the proliferation of new generations of high I/O, fine-pitch surface mount semiconductor package variations, circuit interconnect is an insignificant factor. Circuit board designers continually face challenges such as component quantity and complexity, limited surface area, and meeting the circuit board’s cost target. The printed circuit design engineer’s prominent position demands the development of efficiently manufacturable products that perform without compromise.

Planning the PCB Design
A significant challenge for the designer is overcoming space constraints because of the increasing number of signal conductors, increased component density, and the expanded number of component terminals. This can impede the designer’s effort to create the most efficient circuit routing paths. Circuit routing becomes more challenging as the spacing between terminal lands decreases. With increasing component density and decreasing board area, designers must use extra circuit layers for subsurface routing. Traditional multilayer board construction adds conductor layers in pairs (2-4-6 and so on). However, an excessive increase in circuit layers will affect both fabrication efficiency and manufacturing costs. 

Challenges facing multilayer PCB fabricators include:

• Tolerance control when aligning all layers in the stackup
• Maintaining layer-to-layer registration during lamination
• Consistent thickness control of the finished board
• Avoiding hole breakout when drilling or ablating vias

Here are brief descriptions of three methods commonly used to fabricate multilayer circuit boards:

• Sequential buildup. PCBs begin with the fabrication of a two-copper layer core as a base, followed by layering sheets of partially cured polymer-impregnated (prepreg) fiberglass sheet material between copper foil layers and laminating them under high heat and pressure using a lamination press.
• Multiple core stackup. PCBs combine two or more two-sided copper-clad laminate materials. After imaging and chemical etching of the circuit pattern, workers assemble the two-layer core units with a dielectric glass-reinforced prepreg sheet between core layers, then laminate them under high heat and pressure.
• Multiple core with foil cap stackup. PCBs combine two or more two-sided copper-clad laminate materials. The process follows the steps noted above with an additional layer of prepreg and copper foil on both outer surfaces, simultaneously laminated under heat and pressure.

Figure 1 illustrations represent the multiple-layer circuit board constructions outlined above.

The increasing quantity of signal conductors, increased component density, and the number of terminals on more advanced components will probably restrict the open area on the circuit board’s surface. This can impede the designer’s effort to provide the most efficient interconnect circuit routing. As the spacing between terminal lands decreases, circuit routing becomes increasingly challenging, often forcing the designer to rely on additional circuit layers for subsurface circuit routing. Circuit board fabricators will caution the designer to show restraint with the circuit layer count as well as to implement overly complex layer-to-layer interconnect schemes. The cost can adversely affect the competitive position of the product.

PCB Design Process
With the fabricators’ ground rules established, the next step is to confirm that the designer’s CAD library includes all the parts data and process-proven land pattern geometry. Although the circuit board’s design will continue to include a significant number of passive and single-function low to moderate I/O lead-frame and ball grid array semiconductor packaging, the new generations of high-function semiconductor package families require more terminals and significantly narrower terminal pitch than their predecessors.

The next step is establishing the circuit board’s outline and calculating the basic area for component placement. When estimating the area for circuit interconnect, designers must contemplate the land pattern features for mounting the components, define ‘‘keep out zones,” and establish clearances reserved for assembly process evaluation (and, when necessary, post-assembly rework and repair). Fortunately, software tools have been developed to assist the designer with component placement and include efficient auto-routing features to speed up the interconnect process. The final analysis will provide the designer with an estimated maximum surface area needed to complete all circuit interconnects.

Interconnecting the high I/O semiconductors can dramatically affect the procedures in circuit board design and assembly processing. While a significant number of semiconductor packages will have a moderate level of complexity (I/O and terminal pitch), others may have an excessively high I/O density that restricts conductor routing escape paths. “Channel width” is the term for the space between component attachment areas. The channel widths for routing array-configured semiconductors can be calculated using the terminal pitch (center-to-center distance) and the size of the land pattern. This provides the maximum number of conductors that can be routed between each channel (conductors per channel). When these routing channels are restricted further, the designer will need to consider sub-surface circuit routing to achieve interconnect. The most common solution to conductor routing roadblocks is to adopt blind via-in-land processing, transferring most of the interconnect responsibility between components to the circuit board's sub-surface layers. Adopting blind and buried microvia holes and furnishing pre-defined routing channels will help the circuit board designer route these often very fine-pitch and array terminal configured semiconductor packages.

PCB Fabrication
Circuit board fabrication specialists caution designers that the high-density interconnect circuit board manufacturing process will be more complex than the moderate-density circuit board. To ensure a successful outcome for the HDI circuit board, the designer must consider the manufacturing process complexities and associated costs when implementing the more sophisticated fabrication procedures. The more technically competent PCB fabrication companies can produce conductors as narrow as 25 μm (~0.001"), but they rely on dielectric materials with a very thin copper foil to define the circuit pattern. When conductor lines and space widths must be reduced further, the fabricator will use base materials prepared for a semi-additive copper plating process.

To help the designer establish copper conductor width and spacing for circuit routing, the IPC-2226 specification has defined three HDI circuit board complexity levels (Table 1) for both external and internal locations.

To enable the fabrication of fine-line semi-additive circuits, suppliers will commonly use dielectric materials with very thin Cu foil or use the base materials prepared for the semi-additive copper plating process. Process refinement for HDI PCB manufacturing includes implementing more efficient imaging capability and greater use of alternative hole-forming techniques, applying more advanced etching and plating chemistry, and sophisticated lamination methods.

When possible, establish periodic meetings to review the design with the circuit board supplier as it progresses. This will avoid delays that can affect the product’s introduction to the market. The issues to be resolved are the key attributes, land pattern geometry, and line width and spaces that must be updated to comply with the circuit board fabricators’ capability. This is where the circuit board design specialist should have a pre-release discussion with the supplier to clarify process capability. Circuit board manufacturers commonly give designers practical guidance to help ensure fabrication process efficiency, maximize yield, and minimize costs. Manufacturers have developed these guidelines from experience, and when followed, the circuit board is more likely to be processed without complications. The circuit board designer will be faced with several challenges: component quantity and complexity, limited surface area, and meeting the circuit board’s cost target. Before releasing the design package for a prototype run, ask the fabricator to perform a fabrication process evaluation.

Note that a wide range of PCB design and simulation software tools are available to help the designer avoid potential system failure because of thermal and mechanical loading from growing power dissipation. This is a concern, particularly with smaller board sizes. Analyzing the electrical, thermal, and mechanical characteristics of the board will determine whether the semiconductor package(s) and overall board temperatures remain within safe operating limits and will calculate overall stress conditions that could potentially affect end-product reliability.

Appearances

Vern Solberg will conduct a half-day Professional Development Course, “PCB Design Engineers Introduction to High-Density Semiconductor Package Technologies: 2D, 2.5D, and 3D System-in-Packaging and Ultra High Density Interposer Development,” on March 17 at IPC APEX EXPO 2025.

This column originally  appeared  in the January 2025 issue of Design007 Magazine.