Synopsys, GlobalFoundries Establish Pilot Program to Bring Chip Design and Manufacturing to University Classrooms

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Synopsys, Inc. and GlobalFoundries (GF) announced a new collaboration to launch an educational ‘chip design to tapeout’ program for universities worldwide. Aligned with both GFLabs’ and Synopsys Academic & Research Alliances’ (SARA) missions to advance semiconductor innovation through R&D and academic collaboration, this pilot initiative gives researchers, professors and students hands-on access to real-world chip design and manufacturing. By dramatically lowering the cost barrier to custom silicon, the program enables academic institutions to turn their design concepts into working silicon, expanding opportunities for education, research and workforce development.

Forty universities worldwide are participating in the sponsored open-source 180MCU pilot launching this fall. Synopsys will provide comprehensive support including professional-grade electronic design automation (EDA) tools, training and design collateral leveraging the Synopsys Cloud design platform. Once designs are finalized, GF will manufacture the chips through its GlobalShuttle Multi-Project Wafer Program, which aggregates designs from multiple institutions onto a single wafer for fabrication.

“Partnering with GlobalFoundries to bring a full ‘chip design to tapeout’ course to universities is a game changer,” said Dr. Patrick Haspel, executive director of SARA at Synopsys. “This collaboration will empower students with practical, hands-on experience using advanced tools and technologies – skills that are critical to drive innovation in the semiconductor industry. Together, we’re not just teaching design – we’re building the next generation of engineers who will shape the future of silicon.”

As Synopsys and GF seek to evolve this workforce development initiative further, the next phase of the tapeout is focused on bringing these technologies directly into classrooms and embedding hands-on design and testing into academic course curriculum. With the goal of having students collaborate in a design class, Synopsys will provide training to professors on how to lead this course. Following a shuttle run, the second course will dive into classroom testing with chips returned for the next semester.

“This program reflects our deep commitment to advancing semiconductor innovation and cultivating the next generation of talent,” said Bika Carter, director of external R&D at GF. “By giving students and researchers the opportunity to bring their designs from concept to silicon, we’re enriching chip design education and helping shape the future of our industry. We’re proud to partner with Synopsys to empower the talented minds driving tomorrow’s breakthroughs.”

This design enablement collaboration is supported by Synopsys’ SARA program, which provides software, cloud environments, training and curriculum to equip students with latest technology and learning materials. The new Synopsys-GF collaboration exemplifies the SARA program’s commitment to partner on semiconductor workforce development initiatives and nurture talent pipelines worldwide. Along with providing participating universities with essential tools and cloud environment access, the SARA program will also offer comprehensive course content and training.

The tapeout education pilot is just one aspect of GF’s University Partnership Program, which serves to close the prototyping gap in academia and expand access to new technologies to support technological innovation in the semiconductor industry. In its work with more than 80 universities, 110 professors and 600 students, the program selects projects aligned with GF’s R&D roadmap priorities to support research breakthroughs in areas including radio frequency, radar, quantum computing, silicon photonics, sensors and more.

The combination of Synopsys and GlobalFoundries brings together industry-leading EDA design tools and advanced manufacturing, empowering academic institutions to offer students an integrated, real-world journey through the semiconductor process.