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Impedance Lines: Keep Them on the Inside

Editor's note: This article was originally published in our Inside Design newsletter.Greetings all. In this column, I will be discussing some of the reasons both fabricators and customers may benefit from keeping any impedance-controlled lines on the internal layers.

So, let me dive right in.

1. EMI concerns. If any impedance-controlled lines can be kept to internal layers, the outer layers can have additional shielding by adding additional copper pour. This creates a shield or "can" to minimize emissions. Hopefully, any small transmission lines that must be on the surface layers can be kept to less than 0.3" to 0.5" in length and at this point are most likely not impedance concerns. For those traces on the surface layer that must exist, here the addition of copper pour close to the intended trace can also help to keep the sizes down.

The screen shot below depicts how the addition of poured copper induces co-planar coupling on the surface layers and keeps the trace sizes down.

2. Surface impedances require wider line sizes than those on inner layers, because they only have a reference plane on one side. It is certainly true that dielectric distance between the intended impedance line(s) and the reference plane can be reduced in an effort to keep these line sizes down. There are at least two potentially undesirable effects on the PCB when using thin dielectrics for a microstrip ref plane below .004" in thickness.

Many times, to keep a single-ended line size 0.005 or below on a surface, the fabricator must use a 0.004" dielectric distance or LESS to the reference plane. Most times this means a single ply of pre-preg material.

Depending upon the configuration of the reference plane itself, this reduced dielectric distance can result in things like high resistance shorts. Certainly on a board with a buried plate-up, a single-ply construction of 0.003" or less would not be wise. The additional plating acts as a cookie cutter, slicing through the single ply sometimes resulting in shorting. In addition, from a thermal cycling reliability standpoint, multiple plies of pre-preg are better. 

3. Internal layers are generally printed and etched so that no plating variances can occur as they can on exterior layers. Because of this, tighter tolerances can be achieved, another benefit of keeping impedance signals on interior layers.

To illustrate, let's go back to a time before we routinely used dielectrics of less than 0.004" from a surface layer to a ref plane...

When the 50 ohm line sizes and 100 ohm differential pairs used an approximate dielectric distance of 0.005" to 0.006" to the ref plane, 0.008" lines got 50 ohms rather well as did the 0.005" lines with 0.005" spaces for 100 ohms.

Now that the exterior line sizes are down around 0.0045" to 0.005" the dielectric needs to be thinner to accommodate the 50 ohm structures. This means if the outer-layer impedance lines for both 50 ohm and 100 ohm differential pairs were left at 0.005"/0.005", the differential pairs  would have to be resized to around 0.003" lines with 0.007" spaces for 100 ohms with the thinner dielectric. Not a problem--unless the power was calculated for the wider tracks!

The best solution would be to keep all impedance signals on the inner layers. But that not being an option, a solution we have seen is to have the 0.005" lines with 0.005" space diff pairs reference the third layer down in the stack.

(Create a pass-through of non-metal on the layer 2 plane that is used for the 50 ohm SE transmission lines and add metal as a ref plane on layer 3 for the 0.005"/0.005" diff pairs.)

At approximately 0.007" to 0.008" dielectric distance, 0.005" lines with 0.005" spaces get approximately 100.72 ohms for 100 ohms on standard FR-406 type materials.

These types of solutions are becoming more and more frequent, but at the risk of making an electrical patchwork of varying emissions on the board!

Again, better yet, if all impedances can be kept internal, we find fewer opportunities for impedance mismatches than with both internal and external Impedances of the same value/threshold. An example of this would be that depending upon the layer count versus layer orientation (location of signals versus plane layers) the impedance lines for an external trace of one value most likely will have a different size than those for the same value on an internal layer and therefore perform differently. 

Also, couple that with the fact that internal signals generally do not require an additional plate-up and therefore fabrication variation is reduced. The bottom line is that many designs, though they may be works of art electrically, may not be well-suited for fabrication.

As always, I would say ultimately, for the most reliable product, consult your fabricator for specifics about dielectrics and effective dielectric constants prior to layout to reduce risks.Mark Thompson is in engineering support at Prototron Circuits. Prototron will be exhibiting at DesignCon, so stop by booth #809. To contact Mark, click here.Follow I-Connect007 on Twitter here.