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What is DFM, Really?May 28, 2014 | Mark Thompson, CID, Prototron Circuits
Estimated reading time: 1 minute
Okay, so what is DFM, really? The term "design for manufacturability" has been used for many years now, but does everyone really understand this concept?
For instance, do you design for 10%? Do you design for a specific manufacturer’s capabilities, therefore making you less likely to seek alternative fabricators? How are your drawings worded?
In this article, I will be discussing the reality of DFM and what benefits you, the end-user, by embracing these practices.
Why Design For Manufacturability at All?
Good question. Even if you only buy your boards from a single source--if you have qualified the company already and feel you can expect certain press parameters and dielectric constants based on what they have provided you--it is STILL a good idea to at least design with some latitude. If your design is .1 mm lines and spaces there is not a whole lot of room to either expand or decrease the traces to achieve certain impedances. Clearly, when you have to ingress and egress out of tight-pitch components and your design takes you down to .003”/.003” there is NO ROOM at all for an etch compensation, so you are typically quoted by manufacturers as quarter-ounce foil start. This foil is so thin that we need not compensate for a loss at the etcher like the other copper weights.
Again, as I have mentioned before in my columns, the general rule of thumb is that for every half-ounce of starting copper, you give all the metal features an etch compensation of half a mil. Asking for 1 oz. starting copper, for instance, with 0.003”/0.003” will normally be a no-bid as fabricators would be hard-pressed to be able to run with .002” spaces at Image prior to etch. (Attempting to compensate the 0.003” traces for 1 oz. copper with 1 mil will result in 0.002” spaces at Image prior to etch.) So, 0.003”/0.003” is usually the limit.
Read the full article here.
Editor's Note: This article originally appeared in the May 2014 issue of The PCB Design Magazine.
The "Global Copper Clad Laminates Market (by Type, Application, Reinforcement Material, & Region): Insights and Forecast with Potential Impact of COVID-19 (2023-2028)" report has been added to ResearchAndMarkets.com's offering.
The SCHMID Group, a global solution provider for the high-tech electronics, photovoltaics, glass and energy systems industries, will be exhibiting at productronica in Munich from November 14 – 17, 2023.
The topic of intrinsic copper structure has been largely neglected in discussions regarding the PCB fabrication quality control process. At face value, this seems especially strange considering that copper has been the primary conductor in all wiring boards and substrates since they were first invented. IPC and other standards almost exclusively address copper thickness with some mild attention being paid to surface structure for signal loss-mitigation/coarse properties.
At PCB West, I sat down for an interview with John Andresakis, the director of business development for Quantic Ohmega. I asked John to update us on the company’s newest materials, trends in advanced materials, and the integration of Ticer Technologies, which Quantic acquired in 2021. As John explains, much of the excitement in materials focuses on laminates with lower and lower dielectric constants.
Printed circuit board (PCB) reliability testing is generally performed by exposing the board to various mechanical, electrical, and/or thermal stimuli delineated by IPC standards, and then evaluating any resulting failure modes. Thermal shock testing is one type of reliability test that involves repeatedly exposing the PCB test board to a 288°C pot of molten solder for a specific time (typically 10 seconds) and measuring the number of cycles it takes for a board’s copper layer to separate from the organic dielectric layer. If there is no delamination, fabricators can rest assured that the board will perform within expected temperature tolerances in the real world.