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Beyond Design: How to Handle the Dreaded Danglers, Part 2
October 12, 2016 | Barry Olney, In-Circuit Design Pty LtdEstimated reading time: 2 minutes
In Part 1 of this series, I deliberated on how dangling via stubs distort signals passing through an interconnect and also decrease the usable bandwidth of the signal. This is due to the via stub acting as a transmission line antenna, which has a resonant frequency determined by the quarter wavelength of the structure. The conventional solution to this problem is to back-drill (or control depth drill) the vias to bore out the via stub barrels, so that the via stubs are reduced in length if not completely removed. This month I will look into all the possible solutions to alleviate this issue.
1. Back-drill the stub
Back-drilling is a process to remove the stub portion of a plated through-hole (PTH) via. It is a post-fabrication drilling process where the back-drilled hole is of larger diameter than the original PTH. This technology is often used instead of blind via technology to remove the stubs of connector vias in very thick high-speed backplane designs. State-of-the-art board fabrication shops are able to back-drill to within 8 mils of the signal layer, so there will always be a small stub portion attached to the via.
High-speed, SERDES, serial link-based backplanes generally have thick substrates. This is due to the system architecture and backplane to card interconnect requirements such as press-fit connectors. Back-drilling the via stub is a common practice, on thick PCBs, to minimize stub length for bit-rates greater than 3Gbps (1.5GHz). However, at transmission rates >10Gbps (5GHz), back-drilling alone may not be adequate to reduce jitter and bit error rate (BER).
Figure 1 shows the effects of excessively long via stubs on a high-speed differential pair. On the left, the differential pair is simulated using a pseudo random bit stream (PRBS) with lossy transmission lines enabled; note the open eye pattern. However, on the right, I had included via modelling, which enables the via parasitics and highlights the effects of via resonance. The high-frequency harmonics are attenuated, rolling off the signal rise time, distorting the signal, reducing bandwidth and closing the eye.
Vias can appear as capacitive and/or inductive discontinuities. These parasitics contribute to the degradation of the signal as it passes through the via. At high frequencies and with thick backplane substrates, it is imperative that these issues are addressed.
Back-drilling typically requires specialized equipment, and further requires that the back-drill be precisely located over the vias. As such, the back-drilling process, especially two sided back-drilling, is expensive due to drill breakage and yield issues and is very time-consuming.
To read this entire article, which appeared in the September 2016 issue of The PCB Design Magazine, click here.
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