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Designers Notebook: Embedding Components, Part 7—Semiconductor Placement and Termination Methodologies
Progress in developing high-density embedded-component substrate capability has accelerated through the cooperation and joint development programs between many government and industry organizations and technical universities. In addition to these joint development programs, several independent laboratories and package assembly service providers have developed a number of proprietary processes for embedding the uncased semiconductor elements.
Developers have found that embedding the semiconductors on an inner layer of the PCB or package substrate directly in line with active and passive components mounted on the outer surface ensures that the conductor interface between related components will be minimized.
There are a number of methods used for interconnecting uncased semiconductor components. Semiconductor elements can be mounted onto the core substrate in the faceup orientation or facedown. When placing the die with the active surface of the die facing up, termination will likely adopt copper-plated microvia methodology. Meanwhile, facedown placement will enable the direct interface to land patterns provided on the designated layer of the circuit structure
As noted in Part 6 of this series, the semiconductor fabrication process initially furnishes the die with aluminum bond pads on its perimeter for the traditional wire-bond interface process.
Faceup Semiconductor Termination
Both gold wire-bond and ribbon-bond processes may be applied for completing the die-to-substrate interface. In preparation for this process, a cavity is provided in the substrate (typical of that described in Part 4) to provide clearance for both the die attach and terminal interface. The faceup attachment method traditionally adopts an adhesive material (liquid epoxy or film) for initially attaching the die to the substrate’s surface. Termination lands are positioned on the upper layer of the cavity in line with the wire-bond termination sites on the die element.
To read this entire column, which appeared in the January issue of Design007 Magazine, click here.
More Columns from Designer's Notebook
Designers Notebook: Heterogeneous Interposer Design Challenge, Part 3Designers Notebook: Heterogeneous Interposer Design Challenge, Part 2
Designers Notebook: Heterogeneous Interposer Design Challenge, Part 1
Designers Notebook: Power and Ground Distribution Basics
Designers Notebook: Basic PCB Planning Criteria—Establishing Design Constraints
Designers Notebook: Layer Stackup Planning for RF Circuit Boards
Designers Notebook: Addressing Future Challenges for Designers
Designers Notebook: Impact of Advanced Semiconductor Packaging on PCB Stackup