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Designers Notebook: PCB Design and HD Semiconductor Packaging

To better meet their performance and miniaturization goals, manufacturers are looking for higher functionality for their semiconductor packages. For that reason, many manufacturers will rely heavily on more innovative IC package solutions, often integrating a number of already proven functional elements within a single-package outline. This capability has been stimulated by the rapid deployment of new semiconductor packaging methodologies from a broad number of both domestic and offshore companies that understand that new product time-to-market can be the difference between leading and following.  

The key enablers for providing interconnect for these new generations of multifunction semiconductor elements is choosing the best package substrate or interposer structure for the specific application. PCB designers will realize that the base material and interconnect metalization processes utilized for the traditional multilayer glass-epoxy component mounting base materials are very different from base materials common to semiconductor fabrication. Furthermore, the design rules for via formation and circuit geometry will have a significant difference. On the other hand, these high-density semiconductor package platforms are essentially miniature printed circuits requiring the same tools and skills developed for PCB design.  

The following describes examples of both mature and evolving single-die package variations: 

• Single-die ball grid array (BGA) and fine-pitch BGA (FBGA) packaging 
• Die size and flip-chip package technologies 
• Fan-in wafer-level packaging (FIWLP) 
• Fan-out wafer-level packaging (FOWLP)  

Single-die BGA and the FBGA package families commonly rely on either traditional face-up wire-bond or facedown flip-chip processing for interconnecting to a package substrate. The substrate is designed to redistribute the die terminals on the top surface of the package substrate to a PCB-compatible array contact pattern on the bottom surface. The die elements mounted onto the top surface will be coated or molded over with a polymer composition, and for board-level assembly, alloy spheres or bumps are furnished on the bottom surface.  

Die-size BGA (DSBGA) generally adopts the die facedown approach. The interface between die and interposer may utilize flip-chip processing, but wire-bond and lead-bond processing are more common. A good example of the die-size package using a wire-bond interface is the center-bond memory family of products illustrated in Figure 1. 

Wafer-level Packaging 

WLP technology is commonly utilized to accommodate die elements having very high pin count. Developers have found that by redistributing terminals inside and/or outside the die perimeter, they can accommodate the redistribution on the die terminals to a wider substrate terminal pitch that is more compatible with an organic substrate or PCB circuit routing capability. Silicon wafers are commonly utilized for a broad range of these single- and multiple-die packaging applications, and, although considered an emerging technology, even glass panels are expected to be a viable low-cost alternative to the silicon material. Even though the silicon- and glass-based materials are considered to be an ideal match for HD semiconductor packaging, glass-reinforced B-T epoxy material has been successfully used in manufacturing package substrates for a significant portion of single- and multiple-die packaging markets. Examples of FIWLP and FOWLP are illustrated in Figure 2. 

Preparing die elements for direct chip attachment (flip-chip) to the wafer-level base requires several metalization procedures. While the die elements remain in the wafer format, they are subjected to a rather complex sequence of plating and chemical etching processes to form the conductors and terminal lands required for solder bump or sphere attachment.  

The first process step employs a sputtering procedure to furnish a barrier metal and enable the deposition of a copper seed layer over the active surface of the wafer. A coating of photoresist is then applied over the wafer surface, imaged and subjected to a secondary copper electroplating process to provide the interconnect pattern. After copper plating to form the interconnect pattern and the barrier and seed layer, metalization is chemically removed, leaving only the copper redistribution layer (RDL) ready for passivation and further imaging processes to expose the copper contact pattern for terminal formation.  

Following terminal formation, the die elements are singulated from the wafer format and transferred to systems specifically designed for precise die placement onto the substrate or interposer panel. 2D WLP system-level microcircuits have wide appeal when packaging products require the use of multiple bare die elements from several sources. The semiconductor die elements will be mounted onto the base material facedown (flip-chip) to accommodate reflow solder or alternative joining technologies. Passive elements may also be placed onto the interconnect substrate while in the wafer format. 

System-level Packaging 

Many companies have realized that integrating mature multiple-die elements into a 2D or 3D configured package proves to be superior to a single, multiple-function die (system-on-chip, or SoC) concept because it minimizes risk and significantly reduces both development time and cost. Although integrating several semiconductor functions onto a single die element may appear to provide a viable solution for companies producing products in very high volume, the cost and time required to develop the multiple function SoC semiconductor have often proved excessive. The challenge the developer faces is selecting the chipset that will meet the designated functional goals and choosing a package solution that can achieve the performance objectives and cost constraints.  

3D die-stacking technologies have evolved as a practical, low-risk solution for a number of homogeneous memory and heterogeneous, system-in-package applications. The vertical integration of proven, high-yielding die elements onto a single substrate will enable shorter development cycles and minimize overall development cost. In regard to reaching product objectives, the short interconnect between stacked-die elements will improve functional performance and minimize power, which is a key issue for portable and handheld products (Figure 3). 

3D package-stacking offers practical solutions for pure memory applications as well as mixed-signal and logic and memory applications. Typical applications include the integration of high-density flash, DRAM memory, digital baseband, and processors within a single package outline. Vertically mounting one or more pre-packaged die elements (package-on-package) is preferred by many over die-stack packaging because each level in the stacked package configuration can be pretested before joining (Figure 4). 

2.5D represents a viable approach for integrating very high I/O, fine-pitch semiconductors for both single- and multiple-die package applications. A primary challenge to the PCB design professional is dealing with the excessive increase in the package I/O and the shrinking space between terminals.  

Current examples include a semiconductor die with a terminal pitch range of 40–60 µm (~0.0016–0.0024”) and a terminal geometry as small as 20–30 µm (~0.0008–0.0012”). Although the individual die elements may be furnished with a uniform array terminal format, the terminal size and pitch are often far too small for conventional PCB fabrication capability.  

Users have realized that mounting one or more uncased die elements onto a silicon, glass, or TCE-matching organic-based interposer enables higher-density circuit routing and significantly shorter interconnect for critical signal paths. And with a majority of the in-package interconnect accomplished on the interposer’s surface, the interface between the component(s) and package substrate can be significantly less complex (Figure 5). This, in turn, allows the contact pitch on the package substrate to increase, simplifying the design of the host PCB, more efficient circuit routing, fewer circuit layers, and improved power utilization and ground distribution. 

Key Planning Issues for 2D, 3D, and 2.5D Packaging 

A great deal of progress has been made in semiconductor package process refinement and system development; however, methodologies can vary significantly. Issues that will need to be resolved before initiating package development include: 

• Selection of suitable semiconductors for multiple-die packaging 
• Establishing reliable sources for semiconductor elements 
• Specifying physical and environmental operating conditions 
• Defining package design constraints and process protocols 
• Stipulating electrical test method and post-assembly inspection criteria 

Upcoming Presentation 

Vern will be conducting a half-day tutorial workshop on “PCB Designers Guide to Flip-Chip, WLP, FOWLP, and 2D, 2.5D, and 3D Semiconductor Package Technologies” at IPC APEX EXPO 2020 to be held at the San Diego Convention Center on Monday, February 3. This course addresses the design and assembly challenges for developing and implementing flip-chip and multiple function system-in-package (SiP) technology. To register for this timely tutorial workshop program, visit www.ipc.org. 

This column originally appeared in the January 2020 issue of Design007 Magazine.