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Bert's Practical Design Notes: Perils of Lumped Via Modeling

For years now, the popular opinion has held that PCB vias were mainly capacitive in nature, and therefore could be modeled with lumped capacitors. Although this might be true when the rise time of the signal is greater than or equal to 3x the delay of the via discontinuity, I’ll show you why it is no longer appropriate to think this way. It’s even risky to continue to model your high-speed channel using this methodology.

Let’s start the discussion by assuming vias are transmission lines with excess parasitic capacitance or inductance. Vias are considered transparent when their impedance equals the characteristic impedance of the transmission lines attached to them. In almost all cases, vias passing through multilayer PCBs are capacitive because of the distributed excess capacitance between the via barrel and anti-pads. As a result, they end up having lower impedance than the traces connected to them. Like any other transmission line, when a rising edge of a signal encounters lower impedance, it will cause a negative reflection for the length of the discontinuity.

Getting back to the point, it is best demonstrated by an example as summarized in Figure 1. Consider a via at the far end of a long 50 ohm transmission line. The via has a short through section and a long stub section. The through section is 15 mils and the stub is 269 mils, for a total via length of 284 mils. This is not unusual for modern backplane designs.

For this particular via geometry, the impedance is 33 ohms and the excess via capacitance is 1.9 pf. Even with a fast 50 ps rise time at the source, by the time the signal reaches the via at the far end, the rise time will degrade due to dispersion caused by the lossy dielectric. In this example, after 23 inches, the rise time has degraded to approximately 230 ps.

If the total delay (TD) of the via discontinuity is 60 ps, then the 230 ps rise time at the via is greater than 3TD (180 ps). As expected, when modeling the via with a lumped capacitor equal to the excess capacitance, and comparing it with the transmission line via model, the TDR plot of the reflections are virtually the same using a 230 ps rise time.

Figure 1. Via model TDR comparison after 23 inches. Top topology uses 33 ohm transmission lines for both the through and stub portion of the via. The bottom topology models the via with a 50 ohm transmission line to represent the delay of the through portion and a 1.9 pf capacitor to represent the excess capacitance. Modeled and simulated with Agilent ADS.

So far so good, right? Well maybe so. The only way to know is to explore this topology even further and compare eye diagrams. Let us say your circuit needs to work at XAUI rate of 3.125 GB/s. You modify both topologies by adding a driver and receiver.

After simulating you end up with eye diagrams as shown in Figure 2.

Figure 2.  Eye comparison at 3.125Gb/s. Top topology uses 33 ohm transmission lines for both the through and stub portion of the via. The bottom topology models the via with a 50 ohm transmission line to represent the delay of the through portion and a 1.9 pf capacitor to represent the excess capacitance. Modeled and simulated with Agilent ADS.

Still OK. So, what is your point, you might ask?

You are correct when you comment that there is a good match for reflections and the eyes are wide open. Ah, but now let us say you want to run this topology at 10 GB/s down the road. So you dial up the bit rate on the transmitters and simulate both topologies again. But this time, you get some unexpected results as shown in Figure 3.

Figure 3. Eye comparison at 10Gb/s. Top topology uses 33 ohm transmission lines for both the through and stub portion of the via. The bottom topology models the via with a 50 ohm transmission line to represent the delay of the through portion and a 1.9 pf capacitor to represent the excess capacitance. Modeled and simulated with Agilent ADS.

Ouch! What happened here? Looking at the TDR, the reflections at the end of the channel look the same, so why don’t the receive eyes match?

To answer this question, we really need to look at the S-parameter plots of both channels. Figure 4 shows the insertion and return losses of both topologies. Red is the transmission line via model and the blue is the lumped element capacitor model.

Figure 4. Insertion and return loss of both topologies. Red curves are the transmission line via model and blue curves are the capacitor model. Modeled and simulated with Agilent ADS.

The insertion loss plot represents the transmitted output power vs. frequency while the return loss is the reflected power vs. frequency. In the time domain, the insertion loss and return loss is equivalent to the TDT and TDR plots respectively. As you can see, the return loss matches pretty well; just like the TDR plot we observed earlier, but It is only obvious when we view the insertion loss plot as to the real reason for the eye discrepancy of Figure 3.

Notice the first resonant null at approximately 4.5 GHz. This null represents the quarter wave resonant frequency fo, and is due to the long 269 mil via stub. The other null at 13.5GHz is the 3rd harmonic of fo. The longer the stub length, the lower the resonant frequency. When there is a null at or near one-half the bit rate, then the eye will be devastated. In our example 4.5GHz is approximately half of 10 GB/s and, as you can see from Figure 3, the resultant eye is totally closed.

But the S-parameters tell us even more. We can use them to confirm the rule of thumb used earlier with respect to the rise time of the signal being greater than or equal to 3x the delay through the via discontinuity.

If you study the return loss plot, you will see there is an excellent match up to about 1.83GHz. This is the effective bandwidth for which the capacitor model is good for. Put another way, a bandwidth of 1.83GHz means you could use an equivalent capacitor model for the via for bit-rates up to 3.6GB/s.

Equation 1 is commonly used to convert 3dB bandwidth to equivalent 10-90 rise time. Substituting 1.83 GHz for the 3dB bandwidth, the rise time equals approximately 185 ps.

Equation 1

When you divide 185 ps by 3, you end up with approximately 62 ps compared to approximately 60 ps for the propagation delay through the via we originally determined earlier.

Figure 5 is a summary of a simulation with the transmission line length reduced to 18 inches to reduce the rise time to 185 ps. As you can see the transmission line via model’s eye at 3.6 Gb/s is just starting to distort while the capacitor model is still relatively smooth; confirming our bandwidth rule of thumb. Using a capacitor as a via model past this bit-rate will result in optimistic results and long nights when your 10 gig prototype hits the lab.

Figure 5. Eye comparison at 3.6Gb/s. Top topology uses 33 ohm transmission lines for both the through and stub portion of the via. The bottom topology models the via with a 50 ohm transmission line to represent the delay of the through portion and a 1.9 pf capacitor to represent the excess capacitance. Modeled and simulated with Agilent ADS.

Bert Simonovich was born in Hamilton, ON, Canada. He received his Electronic Engineering Technology diploma from Mohawk College of Applied Arts and Technology, Hamilton, ON, Canada in 1976. Over a 32-year career, working as an Electronic Engineering Technologist at Bell Northern Research and later Nortel, in Ottawa, Canada, he helped pioneer several advanced technology solutions into products. He has held a variety of engineering, research and development positions, eventually specializing in signal integrity and backplane architecture for the last 10 years. He is the founder of Lamsim Enterprises Inc., where he continues to provide innovative signal integrity and backplane solutions to clients as a consultant. With three patent applications and two patent grants to his name, he has also (co)authored several publications, including an award winning DesignCon2009 paper related to PCB via modeling. His current research interests include signal integrity, high-speed characterization, and modeling of high-speed serial links associated with backplane interconnects. To contact Bert, click here.