Estimated reading time: 11 minutes

The European Angle: Institute of Circuit Technology 43rd Annual Symposium

It’s not often we see a radical development in PCB interconnection technology, but Joan Tourné from NextGIn Technology gave an insight into VeCS, a proven alternative approach to Z-axis interconnection which is attracting great interest from OEM designers. He explained that the major limitation of established HDI technologies was the density of vertical interconnections that could be achieved without going through many stages of sequential build-up—an expensive solution. “Why carry on making things smaller—why not make them easier?” In the VeCS approach, the plated hole was replaced by a vertical trace or half-cylinder, enabling the opportunity create more vertical connections per unit area as well as freeing up space for routing conductors. And the vertical conductors could connect to multiple internal layers as required. Additional benefits were improved signal integrity and the absence of paths for CAF.

How was this achieved, and was special equipment necessary? Tourné explained that the basic procedure was to form a slot by a conventional routing operation, and metallise and electroplate it by standard PCB processes, then to drill into the plated slot with a larger diameter drill bit to remove the copper from the areas between the desired vertical conductors. Tool manufacturers could supply router bits designed to minimise burring, and drill-smear problems were avoided because in principle the tool was not withdrawn from the hole it had just cut but was traversed along the slot. Moreover, plating blind slots was more straightforward than plating blind holes of similar diameter and aspect ratio because of better solution penetration and less gas entrapment. So the technology was applicable to any multilayer fabrication facility, with no capital investment required.

Cost savings were realised as a result of reduced layer count for a given interconnection density. If necessary VeCS design features could be incorporated locally on otherwise conventional layouts, for example to overcome fan-out problems under fine-pitch array packages. A further benefit of the VeCS principle was less disruption of internal planes, again improving signal integrity.

VeCS designs were being evaluated by leading OEMs, in cooperation with selected fabricators and assemblers, and EDA vendors were beginning to incorporate VeCS layout capability into their CAD systems.

No visit to the Black Country Museum would be complete without a visit to Hobbs Fish and Chip Shop in the museum’s own High Street. Traditionally cooked in beef dripping and served in newspaper, the lunch-time meal eaten standing in the street gave delegates an authentic taste of the past before returning to the conference room for the afternoon session.

Always eagerly awaited at ICT symposia is market analyst Francesca Stern’s overview of the global PCB and electronics industries. She summarised trends in electronics production world-wide, then individually for Europe, USA, Japan and China. Likewise, trends in PCB production in Europe, USA, Japan, China/Taiwan and Korea.

UK PCB production had shown reasonable growth so far in 2107, but she believed it had now reached a peak and would decline as the year went on, with a further decline in 2018. The market for PCBs in the UK was increasing slightly, but would flatten in 2018 although there would still be a net import. Her figures did not take into account increasing material costs, partly due to exchange rates and partly to supply chain issues. She forecast that European PCB production would peak in 2017 and show slightly negative growth in 2018. The USA would show no growth in PCB production in 2107, but she expected some positive trends in 2018. China and Taiwan were still doing quite well if flex and rigid figures were combined, but the substantial growth was in flex. And Japan was not forecast to see growth any time soon.

Back to the design theme, and specifically to considerations of signal integrity in high-speed designs. Neil Chamberlain, signal integrity product manager with Polar Instruments explored the real-world effect of copper surface roughness on insertion loss, and how it could be quantified as a mathematical parameter in a transmission-line field solver

He explained that whereas DC current was carried uniformly through the cross-sectional area of a conductor, AC currents at frequencies of 10MHz and more were carried mainly in the outer skin of the conductor. As conductors became smaller, the skin effect became more significant and at lower frequencies. “What’s the relationship between frequency and impedance? There isn’t one! But at high frequencies, dielectric loss is the issue.”

Copper foils used in PCB fabrication were deliberately roughened, either electrolytically or chemically, to promote their adhesion to laminating resins. Although “low-profile” and “ultra-low profile” foils were available, they still had some degree of surface roughness and this had a significant influence on skin effect and hence on insertion loss.

PCB designers and pre-production engineers used field solvers for accurate modelling of frequency-dependent PCB transmission lines, to help in choosing appropriate design rules and material parameters. “All models are wrong, but some are useful” was an often-used phrase in the high-speed design community. Chamberlain stressed that effective modelling relied on meaningful input data, and that methods for calculating insertion losses needed to take surface roughness into account. But how could it be measured and assigned a numerical value?

Methods based on mechanically measuring the equivalent number and depth of scratches on conductor surfaces had been used historically, but these were of limited usefulness and only valid for low frequencies. The method proposed by Huray visualised conductor surface topography in terms of pyramids of snowballs and calculated power lost in terms of skin depth and the number and distribution of snowballs in unit area. Simulations had been conducted using different ball radii, and a single effective ball radius had been used to simplify the formula for practical use.

Dennis Price pretended to retire from the industry a couple of years ago, but evidently couldn’t stay away! Recognised and respected for a no-nonsense, common-sense approach, backed by a lifetime of experience, he gave a PCB fabricator’s perspective on Design for Manufacture, which exemplified many of the issues raised in Michael Ford’s earlier presentation.

Acknowledging the range of knowledge, expertise and competence required to be a good PCB layout engineer, amongst them experience of electronics theory, electronic components, circuit diagrams, materials science, PCB fabrication, assembly and test, engineering drawings, engineering specifications, thermal issues, safety rules and regulations and so on, Price described some of the challenges the PCB manufacturing engineer had to address on receipt of the data package.

He discussed the relative cost and yield factors associated with a range of HDI structures, what laminates were specified, and were they the best choice in terms of performance, reliability, availability and cost-effectiveness, the decisions to be made in determining multilayer stack-ups for impedance-controlled designs, and the importance of meaningful fabrication drawings. So much information - and this was in addition to the checking-out of the PCB layout data! He commented that whatever software tools the PCB designer might have used to check his design before forwarding to the PCB fabricator, the fabricator would always run his own DFM checks against his manufacturing capability and resolve any violations or ambiguities before releasing the job for manufacture.

What sort of design features could result in manufacturability problems and potential yield loss? Price showed a whole catalogue of actual examples: drawn features and planes, poor copper distribution and its consequences on plating uniformity, flatness and dimensional stability, poor via hole positioning, via hole in pad issues, component ident on solder joint pads, auto-routing errors and un-terminated tracks, copper slivers and cross-hatch issues, same net spacing violations. And most of these could have been identified and corrected at the design stage with the sort of DFx tools that Michael Ford had described.

Bill Wilkie brought an extremely enjoyable and informative Annual Symposium to a conclusion, thanked Ventec for their sponsorship of the event and invited Martin Cotton to make the closing remarks. Cotton responded philosophically with some thoughts based on Einstein’s “Circle of Knowledge,” which could realistically be applied to printed circuit design and manufacture. Inside the circle was knowledge, outside was ignorance, and the interface between the two was the domain of the enquiring mind. The larger the circle, the larger the interface between knowledge and ignorance. The more that was known, the more was unknown, and the more answers you got the more questions were needed. In Cotton’s words: “Ignorance is bliss: if you know nothing, there’s nothing to learn!”

I am once again indebted to Alun Morgan for kindly allowing me to use his photographs.

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