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All Systems Go: Auto-Detecting Over- and Under-Derated Parts

There are many reasons why a design may fail in the field. How painful would it be if it turned out that a catastrophic failure was caused by a one-cent part, such as an innocuous resistor that was stressed beyond its specified operational parameters? If a product does fail in the field, the costs associated with identifying and remediating the problem can be significant, not least in loss of reputation for the creators and distributors of the device. If only a 1.25-cent resistor had been used in this specific portion of the circuit, thereby saving time, money, resources, and reputation.

Figure 1: A representative schematic of a small analog portion of a larger circuit.

Every component has a primary attribute that the design engineer is looking for. In the case of resistors and capacitors, for example, their primary attributes are, not surprisingly, their resistance and capacitance values. Components also have secondary aspects that must be taken into account during the design process. For example, a resistor’s maximum power rating needs to be considered. For a capacitor, its maximum voltage rating needs to be taken into account.

These secondary limitations might further be dependent on other factors. Temperature can affect the power rating of resistors, while the type of capacitor (tantalum vs. ceramic vs. electrolytic, etc.) can affect how close to the rated voltage a designer is comfortable with the actual voltage reaching. If the voltage at the capacitor is expected to reach 5V, a designer might not be comfortable with a capacitor rated even for say 6V.

This brings us to the concept of derating. To make sure that the component is not subjected to electrical stresses it wasn’t designed for, its value is “derated.” If a capacitor is expected to handle 5V during operations, a capacitor rated to 12V might be used. Derating a component not only helps to ensure the component isn’t subjected to stresses it can’t handle, but it also helps with the longevity of the components. Components subjected to high electrical stresses—even if those stresses lie within the component’s rated value—can reduce their lifespan.

But there needs to be a balance here. While inadequately derating components can lead to unintended catastrophic issues, over-derating parts can be unnecessarily expensive—especially given the number of small parts in an average board. The trick is to derate each device by the appropriate amount.

Now, you might think that if you are armed with the appropriate specification, it would be easy to apply the appropriate derating factors to each component. Unfortunately, things aren’t so simple. Consider a single resistor connected between the power and ground rails. In this case, we know the voltage of the power supply plus some permitted variation (say ±0.1V), and we know the resistor value plus its tolerance (say 1k? ±1%). On the one hand, it’s easy to work out the worst-case current in amps and power in watts. On the other hand, determining whether the wattage selected for the resistor is over-derated or under-derated depends on the operating temperature, and the mathematical relationship between the derating and the operating temperature may be non-trivial. This is just for a single resistor connected between the power and ground rails. In reality, our theoretical resistor would be embedded in a complicated circuit including other components. Determining the voltage and current characteristics of all the components embedded in the heart of such a circuit is much trickier. In turn, this makes the task of determining whether each component is over-derated or under-derated much, much harder.

This sort of analysis requires SPICE-level simulation. Setting up a SPICE simulation for a large number of components can be a time-consuming and daunting task if done manually. That’s not to mention the intimidating fear SPICE strikes into the hearts of many a proud engineer. CAD tools can help here by automating the process of this “electrical stress analysis.” Voltage values are already a part of the schematic data, as are component values. The rest—the current, intermediate voltages, and such—can be calculated by the SPICE simulation. This data can be used to set up and run the simulation “under the hood” without the designer ever having to interact directly with SPICE.

Figure 2: Presenting the results from an electrical stress test.

The time taken to set up, run, and analyze an analog simulation increases dramatically as a function of the size of the circuit being simulated. CAD tools can again facilitate this situation by partitioning large designs into more manageable chunks and by highlighting mis-derated components (possibly by color coding them to easily identify components that are over-derated or under-derated).

When an under-derated part is found, sometimes the solution is not to replace that part. In many cases, a better strategy is to highlight and review the subcircuit containing that part in question. A part coming under unexpected electrical stresses might be caused by the mis-design of other components. Analyzing the entire sub-circuit can help the designer understand if it’s a question of upgrading a specific part or if the entire subcircuit needs to be redesigned. 

Figure 3: Identifying the elements forming the subcircuit of which a problematic component is part.

Derating is a critical topic, but it is often managed with a “sledgehammer” solution. Under-derating risks a dramatic product failure, but over-derating leads to lower profit margins for the products. Appropriate derating requires careful analysis of the entire circuit. Using an appropriate CAD tool able to run an electrical stress analysis, this third option can be a practically viable route and a more precise solution.

Nitin Bhagwath is director of product management, PCB front end at Cadence. Taranjit Kukal is senior product engineering architect at Cadence.

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