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Estimated reading time: 5 minutes
By Martyn Gaudion
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The Pulse: Simplest Stackups Specified
“Everything should be made as simple as possible, but not simpler.” —Albert Einstein
Einstein advocated for describing complex theory in the simplest way possible, but not so simplified that key information is lost. We often see this when the media is criticised for “dumbing down” information. However, from an engineering perspective, if a design can be engineered to perform the required application in a simpler or more economical way, then simplification is truly a valuable goal.
But In the Real World
Often, complex solutions are the only way to realize a design. In these circumstances, the information surrounding a design should be as clear as possible for the people who interact with it during the product’s design and lifecycle.
Small Is Beautiful
It’s also simpler where signal integrity is concerned. Signal integrity becomes more challenging when interconnects are long in comparison to the rise time or maximum frequency component of the signals you are handling. If you keep your traces short enough, then reflections or impedance mismatch become a non-issue; they still exist but the effects are too small to cause trauma to your signals.
For GHz designs, where loss becomes even more of a concern than reflections, the “keeping it short makes it simple” mantra also holds true. With insertion losses being directly proportional to the line length, then halving your line lengths (where possible) will halve your losses: simple and free. I sometimes see questions about line impedance on very short lines, where the frequency of interest is relatively low, and the interconnect at each end of the line is a significant portion of the length. It pays to check whether impedance or loss is an issue in these circumstances. There is a simple Microsoft Excel tool called a critical trace length calculator, which helps check the critical length.
Whilst on the subject of small or short, moving from the X-Y to the Z-axis, the same is true for vias: Keep them short. If you can’t keep them short, keep the stubs short. Let’s drill down (sorry) on all the possibilities for minimising the signal integrity challenges of vias. Remember that, in most cases, the vias are short compared with the trace length unless it is a really thick board.
Thinner boards (where possible) have inherently shorter vias. Where the PCB is necessarily thick because of high layer count, there are several approaches:
- Minimise the stub length
- Use microvias
- Back-drill the offending stubs
Why are via stubs a problem? Simply put, it is because a signal arriving as a stub sees it electrically twice as long as it is mechanically. A signal arriving from the top layer of the PCB traversing down the via to a trace on an inner layer can’t tell the difference between propagating further down the via (the stub) or continuing along the trace, so it does both—the part propagating along the intended trace continues unimpeded. But the part of the signal that chances to propagate down the stub finds an open circuit at the end of the stub and 100% of that diverted signal will reflect and rejoin the main trace, at which point part of the stub reflection will return toward the source and the rest will rejoin the signal headed toward its intended destination. Using buried vias, back-drilling the stub, or using microvias are all technical solutions to this, but an alternative is to (where possible) route so that the stubs are as short as possible—say, on a 10-layer board route a signal from L3 to L8 rather than L1 to L5, which would leave a far longer stub. Sometimes a rapid check to see whether a feature, such as a stub, is a cause for concern can rapidly put you at ease or flag if more attention is needed. Figures 1, 2, and 3 depict differing stub lengths and their relative impact, from “safe to ignore” (green 28-mil stub) to “do something about it” (red 200-mil stub)) when the stubs are in a 4Gbit/s data channel.
Modelling Single-ended and Differential Via
Modelling vias is one of the most frequently searched terms driving traffic to the Polar website. One of the counterintuitive points on via modelling is that it is easier to obtain an estimation of a differential via’s characteristics than that of a single-ended via. Why? Because differential vias are inherently an out-and-return path, there are no discontinuities in the return path (or at least they are minor) compared with single-ended vias. This is a key advantage for designs with ultra high-speed digital signaling in making them easier to design. While you can model a single-ended via with a 3D solver, it only goes to prove the design is compromised. To get the best signal integrity for a single-ended via, it can be necessary to place it next to a ground via which spans all the intermediate planes. Plane pairs to single-ended vias act as slot antennae and cause reflections out and back to the edge of the board. Transitioning a signal from L1 to L3 with a ground on L2 would minimize this, but at same time, you have to check that the stub is still short enough not to be troublesome.
Once your stackup design is completed, then ensure it is documented and make it clear to your fabricator, broker, or shop floor that you are a PCB apps engineer so that drills/back-drills, layer separation, and any transmission lines are clearly identified and associated with the relevant net classes.
Keeping high speed line length as short as possible, stubs short, and careful attention to via interconnects can ease your signal integrity challenges at minimum cost. Use simple tools to flag areas where more detailed modelling or more advanced materials may prove necessary and remember that in most cases engineering is about delivering to your employer and customer the most appropriate solution for the specific application at the lowest cost. Find more information about signal integrity on our website and YouTube channel.
This column originally appeared in the November 2023 issue of Design007 Magazine.
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The Pulse: Instilling an Informal Information Culture
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The Pulse: Field Solver Finesse for Modelling Transmission Lines
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The Pulse: Fake Fudged Facts—Using Software to Get the Right High-Speed Answer
The Pulse: PCB Design Education—What ‘They’ Don’t Tell You