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Trouble in Your Tank: Materials for PWB Fabrication—Drillability and Metallization

Laminate materials are the building blocks on which printed circuit boards are manufactured. Circuit board designers rely on the critical electrical properties of the materials to design the interconnects, and with the drive toward IoT (internet of things), autonomous driving, and virtual and augmented reality, material properties take on a very high level of importance.

The crux of the issue is quite simple: Designers are looking for electrical performance. Printed board fabricators are concerned with manufacturability and yields. As the complexity of circuit technology increases (and it won’t stop anytime soon), there will be continual pressure to improve yields. However, that is the conundrum or the cliché of a rock and a hard place.

Let’s consider the requirements for high-speed data transmission. The system designers are examining several factors, most importantly signal speeds, loss characteristics, and laminate selection.

Laminate Selection: Dk and Df
The Dk is the property that determines the relative speed at which an electrical signal will travel in that material. A low dielectric constant will result in higher signal propagation speed, while a high dielectric constant results in lower signal propagation speed, i.e., the lower the Dk, the less impedance there is to the signal propagation. The characteristic impedance of a printed circuit board is determined by the thickness of the laminate and its Dk. Impedance control and impedance matching of critical linked functional modules become especially important in very high-speed, i.e., high-frequency designs. Dk also tends to shift with temperature so heat generation by such designs is another important factor.

The Df (loss tangent) of the material is a measure of the percentage of total transmitted power that will be lost as power dissipated into the laminate material. High frequency signals switch backward and forward rapidly. There is the switch between positive and negative, causing the molecules within the resin (dielectric) materials to polarize with the electromagnetic field of the signal.

During this situation, there is heat loss. Thus, there are signal losses that become greater at higher frequencies. These losses are proportional to frequency and become more pronounced at frequencies higher than 10 GHz. However, today’s technologies require signal speeds in excess of 35 GHz for selected applications; at 35 GHz and above, everything matters. Skin effect is real and must be considered as higher frequencies are used as part of the main-stream circuit designs going forward.

So, what does all this mean? From a simplicity standpoint, these higher performance materials are much more difficult to process for the PWB fabricator. Basically, it is not your father’s FR-4 anymore. From a fabrication standpoint, processing a 140°C Tg material through the desmear/etchback process, as an example, is much easier to etch the resin, remove drill smear, and create sufficient topography to enhance the adhesion of the plated copper. Higher performance materials are not easy to desmear and metallize.

As one moves up the laminate material technology curve (lower Dk, lower Df engineered materials including ceramic-filled), resin removal or simply etching the resin becomes more difficult. For the fabricator, this necessitates a change in the mindset related to chemical desmear. If the end user is requiring a significant amount of etchback, this may not be practical with current mechanical and chemical set-ups. The fabricator must resort to radical departures from the status quo. This includes extended dwell times in the desmear process, increasing the aggressiveness of the chemistry, and use of plasma etchback as either a stand-alone or in combination with chemical processing. Satisfactorily, bare board fabrication now includes a variety of materials. Glass-reinforced laminate for rigid printed boards and unreinforced laminates, used primarily for flexible printed boards, present significant challenges for desmear/metallization as well as in lamination. Further, these higher-performance, thin-core materials are being combined in a variety of applications to achieve a thinner profile of the end product. Thus, lamination of the combined materials (including adhesives) requires changes in the lamination cycle parameters, including time, pressure, and heat rise rate.

There are several additional material properties that the PCB fabricator must consider to optimize the process. For consideration:

Drillability and Metallization
Drillability is an important consideration in selection of a laminate for a backplane, particularly with high plated through-hole aspect ratios and the increase in backdrilling. Constant diameter and clean finish are essential. The grade of glass fiber, fillers, and dielectric material hardness all contribute to the hole quality.
Ceramic-filled materials can also introduce extra cost in fabrications. The ceramic can reduce the lifetime of a drill bit from 5,000 to 500 hits.
There are concerns with hole wall quality as fabricators move up the material technology curve. Most notably is rough drilled holes along with deep gouges (Figure 1).

Figure 1: Rough hole walls after drilling.

Drill quality or lack thereof (Figure 1) affects several aspects, including solderability, plating adhesion, and potentially component insertion. Regardless, the higher-performance materials are more difficult to drill. Hole wall roughness must be reckoned with.
Monitor the number of hits each drill bit is subjected to. Be concerned that these higher-performance materials will cause the drill bit to wear out faster. In addition, adjusting spindle speeds and infeed rates must be considered to ensure good hole wall quality.

Metallization
As mentioned previously, these materials provide significant challenges to the fabricator. The process step of providing a void-free, tightly adherent copper deposit to all surfaces (resin, glass, copper) is paramount in achieving plated through-hole reliability. Any issue that compromises the copper plating uniformity and adhesion will lead to defects, including plating voids, hole wall pullaway, and interconnect separation. Not a good thing.

So, as these higher performance materials are more difficult to desmear and form any reasonable topography on the resin materials, adhesion of the plated copper is a concern. What should the fabricator do in this situation? One option is to use an electroless copper process that deposits the copper at a slow and steady deposition rate. One may call this low-to-medium deposition electroless copper. The way the copper grain structure forms during the metallization process really does matter. Low internal stress of the deposit is beneficial in improving adhesion to the various materials that make up the circuit board. Slow and steady wins the race. Monitor the deposition rate of the copper. I prefer 1–1.5 microinches of electroless plating per minute. In this scenario, the copper deposit will be much more uniform and of lower stress.

A second critical point is to not over-catalyze the surface with palladium. Excessive palladium, while great for initiating the electroless copper, will lead to a spongy-looking deposit that will exhibit poor adhesion. Excessive palladium acts as a barrier, preventing the plated copper from making intimate contact with the resin and copper surfaces.

This column originally appeared in the June 2024 issue of PCB007 Magazine.