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StratEdge Brings Gold Medal Performance with its Molded Ceramic and Post-fired Ceramic Packages, and High-reliability Assembly Services
August 14, 2024 | StratEdgeEstimated reading time: 1 minute
StratEdge Corporation is redefining the landscape of semiconductor packaging with its cutting-edge molded and post-fired ceramic packages, supported by industry-leading high-reliability assembly services. Engineered to meet the rigorous demands of modern applications, StratEdge's innovative solutions are tailored for markets including telecom, wireless, satellite, defense, and beyond, ensuring unmatched performance in the most challenging environments.
StratEdge's molded ceramic packages offer unparalleled reliability, designed to handle high-frequency chips up to 18 GHz, with over 200 standard outlines available, providing a vast array of packaging options. Complementing these, StratEdge's post-fired ceramic packages excel in thermal management for compound semiconductors like GaN, GaAs, and SiC, operating from DC to 63+ GHz. The packages provide ultra-low loss performance over a wide range of frequencies, depending on the style and mounting configuration. Many open-tooled designs are available with 50 ohm impedance high-frequency transitions, which provide convenience and ease for packaging high-performance semiconductors.
StratEdge's ISO 9001:2015 certified facility features a Class 1000 cleanroom with Class 100 work areas, for performing sensitive microelectronic assembly. It’s equipped with state-of-the-art assembly equipment, including a device bonder with a eutectic gold-tin (AuSn) attachment station that achieves bond line thicknesses of 6µm. This refined eutectic die attach technology maximizes power output for GaN devices, resulting in lower junction temperatures and increased device reliability.
"We manufacture our high-frequency packages with precision, using post-fired ceramics with laser-cut features to control tight tolerances, thermally-enhanced metal bases that dissipate heat, and electrical transition designs that provide exceptionally low electrical losses," explained Casey Krawiec, VP of Global Sales at StratEdge. Krawiec continued, "Working with compound semiconductors, such as GaN, requires a package that can best dissipate the heat from the device while ensuring optimal performance. Although the package plays the most critical part, the way the chip is attached can also make a significant difference in the device's performance."
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Unlock Unmatched Performance for Matched Impedance Devices with StratEdge at IEEE BCICTS 2024
10/22/2024 | StratEdgeStratEdge Corporation, an industry leader in high-frequency and high-power semiconductor packaging, is excited to announce its participation in the IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS).
TopLine to Exhibit 'Drop-in Replacement' for BGA at Electronica
10/16/2024 | TopLineTopLine Corporation will exhibit its latest technology solutions at Electronica in Munich, Germany, November 12 – 15, 2024, in stand B4.428.
PCB Surface Topography and Copper Balancing Under Large Form Factor BGAs
10/01/2024 | Neil Hubble, Akrometrix and Gary A. Brist, Intel CorporationAs CPU and GPU packages grow larger and contain higher pin/ball counts, the importance of managing the printed circuit board (PCB) surface coplanarity for package assembly increases. The PCB surface coplanarity under a package is a product of both the global bow/twist of the PCB and the local surface topography under the package. In general, the surface topography is dependent the choice of material and layer stackup and the interaction between the innerlayer copper patterns and prepreg resin flow.
StratEdge Semiconductor Packages Set to Take the Spotlight at European Microwave Week and IMAPS Symposium
09/11/2024 | StratEdgeStratEdge Corporation announces that it will be exhibiting in booth 923B at European Microwave Week (EuMW), being held at Porte de Versailles Paris, France from September 24-27, and booth 313 at IMAPS International Symposium for Microelectronics being held at the Encore Boston Harbor in Everett, Massachusetts, on October 1-2.
Reliability Comparisons of FPBGA Assemblies Under Hot/Cold Biased Thermal Cycle
08/06/2024 | Thomas Sanders, Seth Gordon, Reza Ghaffarian, Jet Propulsion LaboratoryCurrent trends in microelectronic packaging technologies continue in the direction of smaller, lighter, and higher density packages. The telecommunications industry and particularly mobile/portable devices have a strong need for lighter and smaller products. The current emerging advanced packaging (AP) technologies, including system-in-package (SiP) and 2.5D/3D stacked packaging, added another level of complexity and challenges for implementation.