Estimated reading time: 4 minutes

Part 1: PCB Designers Notebook: Microelectronics and SMT

by Vern Solberg

Portable and wireless electronics represent the most aggressive growth area for high-density PCB technology. In both circuit-board fabrication and IC packaging, the technology for compressing even the most sophisticated electronic functions into a smaller, lighter finished product continues to evolve. To reduce product size, many companies have selected passive and active surface mount components with the smallest available outlines, and have even adopted the use of a number of uncased die within the SMT design. Two methodologies can be considered for mounting uncased die: chip-on-board (COB) and flip chip (FC), or direct-chip attachment.

Chip-on-board Process

Bare die initially are attached with the active surface facing upward, and use a gold wire-bond process for die-to-substrate interface. Before proceeding with the die-attach and wire-bond processes, the area must be cleaned - plasma cleaning is common - to ensure a reliable die-attach and wire-bond interface. In addition, the adhesive selected for die attachment must not affect the mechanical integrity of the circuit conductors on the board's surface adversely, or the integrity of the electrical signal it covers. Following die-attach and adhesive-curing processes, the die is ready for electrical interface to the substrate base. The wire-bond pads on the die are individually connected to gold-plated bond pads on the substrate using very thin gold or aluminum wire, where feasible. Following the wire-bond process, the die and bond area typically is protected by encapsulation or conformal coating. A liquidus encapsulation material can be applied using a dispensing system, while the conformal coating typically is applied with a spray or dip process that covers all components. An alternative to encapsulation over the individual die-mounting area is the post-assembly attachment of a pre-molded cover.

Flip-chip Process

An alternative to wire-bond technology is the flip-chip mounting process. Flip-chip (or direct-chip-attach) design eliminates the need for wires and die-attach adhesives. For this application, die wire-bond sites are prepared with alloy bump contacts. The bump contacts generally are applied before dicing (wafer sawing), while the die remains in the wafer-level format. Die-bond pads, however, are not immediately compatible with either solder or the conductive-adhesive-attachment processes. Solder bumping with a solder-compatible alloy composition is one of the most common procedures. The solder material and the bumped-pad structure materials are chosen to optimize electrical and mechanical connections.

For attachment, the pre-bumped die is flipped - active face down - onto mating lands on the circuit substrate using solder or conductive adhesive. This alloy bump, or ball, is applied to the die-bond pads by either a thick plating process or placement of individual preformed ball contacts. Both processes require mass reflow to complete the joining and forming of the finished ball or bump contact. Of course, the alloys selected for bumping the die must be compatible with the solder composition used on the mating substrate.

Conductive adhesive or polymer attachments can be adapted as well; however, when conductive polymers are used, the die-bump contact may require a “noble” alloy that is compatible with the conductive-alloy particles in the adhesive. Gold-alloy bumps are common for this process. Gold-alloy contacts generally are applied using electroplating or a common wire-bond system. In this case, the wire is snapped off at the top surface of the basic bond mass, leaving a reasonably uniform bump feature. When using solder or an isotropically conductive adhesive, the gap (standoff) between the die surface and the substrate surface likely will require an under-die filling with epoxy to ensure mechanical integrity of the die-to-substrate interface.

Design features for attaching the uncased die and other surface mount devices are quite small; the trend is to place them as close together as practical. For example, 50-µm line-and-space circuit features are becoming commonplace for these applications, as are laser-ablated and plated vias. As I/O counts on the silicon die increase, and the demand for smaller electronic products continues, industry roadmaps predict that pressure remains to further reduce conductor features on the board and module substrates.

Conclusion

To review a broad picture of what the industry trends will be, consider information supplied in IPC and iNEMI roadmaps. The IPC International Technology Roadmap focuses on the interconnection industry, while iNEMI’s Technology Roadmap focuses on the business and technology areas associated with the electronics’ industries global supply chain. My next column will study the specific requirements for assembly of die attach and wire bonds, the assembly sequence for surface mount devices, process parameters for fabricating a board, and characteristics pertinent to increasing component interconnection complexity.

Vern Solberg,SMT Advisory Board Member, is the senior applications engineer and technical advisor to in-house and OEM engineers and specialists at Tessera Technologies Inc. Additionally, Vern holds several patents for IC packaging innovations and is a member of many industry standards organizations, including IPC, SAC, IEC TC91, and the JISSO International Council. He may be contacted at (408) 568-3734; e-mail: vsolberg123@aol.com.