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PCB Designers Notebook: SMT Land Patterns for Lead-free

by Vern Solberg

Designers have expressed concern regarding the impact of the lead-free soldering process on the SMT land-pattern geometry furnished on existing and future circuit board designs. In general, if the assembly process has exhibited satisfactory yields with lead-bearing alloys, the board design and land-pattern geometry does not require modification for the lead-free alloy. Therefore, the designer and the assembly-process specialist should review the land-pattern library occasionally. Many have observed that lead-free SAC alloys have different wetting and capillary characteristics than those of eutectic tin/lead alloy compositions. The SAC alloy, while in its liquidus form, does not exhibit the same flow or migration across the land and onto component terminals as the tin/lead alloy. Many have also found that the self-centering and self-aligning phenomena of smaller components and BGAs normally experienced during tin/lead soldering cannot be assumed. On the other hand, because melted solder flow is contained within the printed area, bridging between closely spaced features or into adjacent plated via holes will be minimal.

Many CAD software suppliers furnished a basic library of parts based on early component-package technology and assembly-process capability. A growing number of devices are now available that may not have existed when the library was originally developed. These newer generations are designed and manufactured using metric dimensioning. The fine-pitch BGA (FBGA) and fine-pitch no-lead devices, for example, are lead-free-solder compliant, but have very close contact-pitch and contact-geometry tolerances. Even the slightest deviation in land-pattern spacing will likely compromise manufacturing yield and impact product reliability. Miniature 0102 and smaller passive devices have also proven to be a challenge for assembly. It is not uncommon to observe excessive contact-to-land separation during reflow soldering. The solder overwhelms the tiny particle-size device, and the wetting and surface tension cannot overcome the affect of solder cooling at even slightly different rates. Another contributor to contact separation is the topography of the attachment site. Smaller devices have smaller spacing between contacts. To avoid any teeter-totter effect during reflow, and assist in maintaining equal surface tension of the solder between opposing contacts, avoid using a solder mask under these devices.

With regard to dimensioning, land-pattern libraries for SMT components were furnished or developed initially using the English measurement system. Experts are concerned that a metric-to-inch conversion exercise is not exact, and may actually compromise solder joint integrity on higher-pin-count devices. Developing a unique all-metric library of land patterns will not be a welcome chore, and many designers will continue to resist adopting metric dimensioning. The IPC encouraged designers to adopt the international dimensioning format early on, and developed the original IPC-SM-782 Surface Mount Design and Land Pattern Standard. This document became a popular source for designers, but due to the increasing growth of new component families and rapid development of active component package variations, it was not able to maintain concurrence. Addressing this issue, the organization sponsored a task group of seasoned, industry experts to develop a new two-part document to guide designers through the land-pattern-generation process and furnish a method for updating existing component families, as well as adopting new component families quickly. The IPC-7351, Generic Requirements for Surface Mount Design and Land Pattern Standard was developed to provide guidance on land-pattern-development criteria, and furnish optional geometry variations for higher-density electronic applications. This standard provides practical guidance in developing land patterns for surface attachment of electronic components. The intent is to offer the appropriate size, shape, and tolerance of surface mount land patterns, and ensure that sufficient area is recommended for the appropriate solder fillet. It also aims to maximize assembly process compatibility. Developed in parallel, a companion document and software designated IPC-7153A provides an Internet-accessible viewer and calculator program. The viewer program can be used to research and develop SMT land patterns and includes most common device families in the commercial market. The calculator is a tool designers can use to format a land pattern by entering the mechanical features of a specific device, adding anticipated fabrication and assembly process tolerances, and include required features such as silk-screen legend and fiducial targets or solder-stencil apertures. The online system calculates all geometries automatically and furnishes the complete pad-stack ready to download into the designer’s CAD library. The latest version of the viewer and calculator can be accessed at no cost at www.pcblibraries.com, and includes a RoHS-compliant, lead-free land-pattern section detailing some features that may contribute to a robust assembly-process yield and enhance product reliability.

Vern Solberg, SMT Advisory Board Member, is a consulting engineer specializing in surface mount and microelectronic design and manufacturing. Additionally, Vern holds several patents for chip-scale and 3-D IC packaging innovations, and is an active member of many industry standards organizations, including IPC, SMTA, IMAPS, and the JISSO International Council. He may be contacted at (408) 383-3614; email: vsolberg123@aol.com.