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All Systems Go!: Thermal Compliance of 3D-IC

The modern world of advanced multi-chip packaging has evolved over the years in a very subtle way. Today's advanced IC packaging is about adding value to end products. Electronic product design companies are leveraging packaging technologies to create value and differentiation from their competitors. In the packaging world, we have been designing heterogeneously integrated multi-chip products for decades. As we know, smaller process nodes enable higher frequencies and save on die area. However, for minimizing the system size, we need to use advanced packaging technologies. 3D die-stacking technology has emerged as a viable solution to overcome the yield issues with larger dies. Through-silicon via (TSV) is a disruptive technology for 3D die stacking with better performance, dense inter-die vias, and smaller package form factor. 3D-ICs with TSVs have a broad impact in areas such as networking, graphics, mobile communications, and computing, especially for applications that require ultra-light, small, and low-power devices.

Figure 1: An example of a 3D stackup.

Some of the packaging platforms that come under the three-dimensional integrated circuit (3D-IC) umbrella are 3D stacked ICs (3D-SICs), 3D wafer-level packaging, monolithic 3D-ICs, 2.5D, and 3D interposer-based integration, 3D systems integration, and 3D heterogeneous integration. 3D-IC packages accommodate multiple heterogeneous die—such as logic, memory, analog, RF, and micro-electrical mechanical systems (MEMS)—at different process nodes, such as 28nm for high-speed logic and 130nm for analog. This provides an alternative to system-on-chip (SoC) integration, potentially postponing an expensive move to a new process node for all the functionality developers want to place in a single package. For these reasons, the semiconductor industry has embraced the entry of 3D-IC with much enthusiasm.

We can consider this change as helping to add more features to the chip. Demand for better power, performance, lower cost, on-chip communication, and heterogeneous integration boosted package devices in 3D format. The key innovation factor in 3D-IC is the reduction in the length and width form factor. The traditional packaging methods can integrate only in the length and width, which need a large surface area. But when components are vertically stacked up, surface area reduces and thereby the form factor.

Thermal challenges in electronic designs are not a new topic. As we know, thermal effects limit the maximum operating frequency as increased electrical content logically generates more heat which in turn affects the system performance. If this is the situation of a traditional package, can you guess the thermal impact on a 3D-IC?

The smaller geometries and higher frequencies increase susceptibility to thermal effects. The heat generated must be adequately dissipated for optimum performance. The thermal challenges of 3D-IC are exacerbated due to the stacked architecture. Multiple dies on single package will have both performance and reliability challenges due to not only self-heating, but also mutual heating. Further, the substrate thinning required for 3D stacks results in relatively poor heat dissipation. It is crucial to have a thermal signoff methodology to ensure the device is meeting its power and performance requirements under thermal constrains.

Moreover, to facilitate TSV connections, the wafer is thinned to implement a 3D-IC. This process not only causes stress but adds additional thermal challenges. The heat generated can cause significant design problems, such as thermal runaway, which can melt down the silicon. The question is, how do we predict the thermal impacts earlier in our design cycle?

The thermal analysis looks at the impact of power and heat generation across components of electrical devices. Thermal management is critical as even a slight thermal variation can result in permanent damage or malfunctioning of the device. At the design level, it can cause late-stage design modifications and iterations and derail project schedules. For a complex 3D-SIC structure, it is important to know the operating temperature of the individual chip to estimate its electrical performance. Analyzing the chip thermal flow out of the chip and its impact on the electrical performance is an important step in the early design.

Further, we know that the chips in a 3D structure have various power profiles depending on the required workload and, due to this, they have different thermal behaviors. Therefore, having an accurate power profile for thermal analysis is a must. Along with the chip, package thermal behavior is important to determine the IR drop and performance of the system. However, for package performance analysis, it is important to combine both electrical and thermal analysis and simulate the flow of both electricity and heat for a more accurate system-level thermal simulation.

The complex chip architecture with greater power density, time-consuming thermal transient analysis techniques must be deployed together with traditional steady-state analysis to address multiple power profiles and increased heat dissipation. Further complicating the process, traditional thermal simulators require simplified models of the electronics and enclosures, resulting in reduced accuracy. We need a tool that can perform end-to-end analysis, unlike traditional tools that can handle only chunks of the design or perform static analysis. 3D-IC packaging faces tremendous thermal challenges and requires a tool that can perform both static (steady-state) and dynamic (transient) electrothermal co-simulation based on the actual flow of electrical power in advanced 3D structures, providing visibility into real-world system behavior.

Melika Roshandell is a product marketing director for the Multiphysics System Analysis Group at Cadence Design Systems. 

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The System Designer’s Guide to… System Analysis: Electromagnetic Interference and Thermal Analysis of Electronic Systems

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