Estimated reading time: 14 minutes

A Walk on the Technical Side: SMART Group's 2012 European Conference

Thame, a charming old market town close to the Chiltern Hills in the county of Oxfordshire, UK, was the venue for SMART Group’s 2012 European Conference. As always, Technical Editor Pete Starkey made the trip for I-Connect007 and reports, in his usual, amazing detail, the presentations given, new information revealed, and areas of study.Introduced by SMART Chairman Keith Bryant, the conference programme occupied two days of technical presentations and networking sessions. Having greeted certain American guests with his customary irreverence, Bryant made special mention of Technical Committee members Bob Willis and Richard Boyle, who had recently given up their time to volunteer as Olympic Games Makers, inviting them to pose for photographs clad in their official regalia.Dr. Steve Jones, founder of Printed Electronics Ltd., gave the keynote presentation, “Digitally Printed Electronics – What will it deliver?” His company was concerned with integration, process, and product development, working on inkjet techniques for electronics and material deposition. The company was now seven years old and Dr. Jones readily admitted that most of the first five years had been spent understanding how little knowledge really existed, and particularly that there was no supply chain for printed electronics materials and processes. “Why printed electronics?” Dr. Jones’s benchmark was the highly-established subtractive process of printed circuit manufacture, based on photolithographic imaging which was capable of routinely resolving 100 micron lines and spaces, but which had a high capital cost and a generated a high waste stream. “Change is good," he remarked with reference to the ink jet techniques presently being introduced to the market by companies like Mutracx and MicroCraft which, by direct digital deposition of etch resist, could potentially make a substantial reduction in the number of process steps and save a lot of space in the traditional photomech department. But this was not printed electronics. It did not change the fundamental subtractive nature of the technology. Printed electronics opened up a whole new spectrum of opportunity for creative lateral thinking. Products didn’t have to look like conventional electronics, provided they brought out the attribute the customer wanted. PEL’s Material Deposition System was capable of depositing 4-colour graphics and functional materials in combination, giving the opportunity to mix graphics with electronics. Other potential applications included the printing of multiple electronic elements in a linear pass, the printing of chemically reactive species to form chemical reactions on a substrate, and the printing of biologically active materials.“What’s in the toolbox?” Dr. Jones answered his own question: Conductors and dielectrics for printed circuits, conductive adhesives for “solder joints,” passives components, such as resistors, capacitors, and inductors, and active components such as transistors, memory, and displays, as well as batteries and switches. Additive manufacturing using printing of electronic components was a young, but capable, technology. End products that could be made using discrete components were an ideal fit for the current technology, adding value by adding function, enhancing performance, and putting electronics into new and exciting places. Dr. Jones was under no illusions: “Remember that the established electronics industry is extremely capable and has low cost structure, so to simply remanufacture existing products is not the way forward. We don’t want to compete, because we can’t. But we can do things others can’t do.”Dr. Jones having provided an insight into a parallel world of alternative electronics and innovative applications engineering, the main content of the conference focused on reliability issues, and a couple of familiar faces came into view--no SMART Group Conference would be complete without a contribution from the Doug and Dave Roadshow! Jet-lagged failure analysis guru Dave Hillman, half of the renowned Rockwell Collins double act, described an investigation of thermal-cycle solder joint reliability of BGA connectors for high performance products. To satisfy the ongoing requirement for connectors with higher I/O density, various configurations based on BGA termination were now available and Hillman had been tasked with determining whether they represented a reliable option for avionics applications. Looking back at some of the problems historically associated with leadless ceramic chip carriers, he remarked, “Those who ignore the past are doomed to repeat past mistakes,” and commented, “Solder doesn’t like shear!” Although the potential problems associated with CTE mismatch were not expected to be as critical with BGA connectors as they had been with LCCC, their behaviour under thermal cycling conditions would be a good indicator of their reliability.An experimental plan had been designed around a 2mm thick 12-layer FR4 PCB with ENIG finish as the test vehicle, and eight different styles of connector had been evaluated. All were assembled with eutectic tin-lead solder, and some further samples with SAC 305 for comparison. All were subjected to 1,200 thermal cycles of -55ºC to +125ºC, with 8-10ºC per minute temperature rise and 15-minute dwell. The interconnection integrity was monitored as the resistance of a daisy chain and failed assemblies were microsectioned to examine the failure mechanism. It was clear from the results that the performance test conditions exceeded the capability of many BGA connector designs and that those configurations incorporating compliancy mechanisms or which made provision for additional solder volume gave better performance. Non-traditional connector solutions appeared to be a viable option for some programme applications, and soldering was not the only answer. Hillman concluded that not all BGA connector configurations were appropriate for high-performance applications and that testing was required, either programme qualification or technology qualification.From failure analysis guru to stress specialist: Andy Stiles from Aero Engine Controls gave an insight into design for vibration as he discussed the mechanical de-risk analysis process of electronic systems, with reference to engine management systems for jet engines. A typical electronic engine controller weighed about 20kg and was attached to the outer casing of the engine on anti-vibration mounts, which were carefully selected to give the system a natural frequency in a “quiet band” based on spoke diagrams and vibration profiles. The dynamic design of the electronic engine controller was broken down into three bands: The rigid body modes or natural frequencies of the anti-vibration mounting system, which were normally sub-100Hz, the longitudinal, lateral bending, and torsional modes of the main panel, typically in the range 300-500Hz, and the local card modes, which were normally above 700Hz. The initial design analysis, covering anti-vibration mount selection, chassis characteristics, card thickness and column spacing was carried out at sub-model level to speed up design iteration time. Each of the cards was modelled with appropriate properties and data recover points defined, and in some cases individual components were modelled. Attention to detail was painstaking and meticulous. A typical full system model included about 200,000 finite elements with 400,000 nodes and, when the complete model was run with the appropriate load, the results files amounted to 10 to 20 Gb of data. To satisfy the aviation authorities, the analysis even had to consider worst-case scenario of a fan-blade-off event, and the effect on the controllers on the aircraft’s remaining engines during the limp home to the nearest landing opportunity.Mechanical reliability was the speciality of Bob Page from ReliabilityPlus, and his presentation “Smart HALT” referred not to SMART Group but to the Smart Car, and specifically to the Smart ForTwo HD electric town car project and how highly accelerated life testing had been used as an approach to studying the robustness of its drive train electronics. Specifications and standards for reliability had historically been based on environmental simulation of generic worst-case operational conditions. Page believed that design robustness was the key to reliability, which was determined by the number of latent design defects, the reliability of the components from which a product was built, and the number of latent manufacturing defects in the delivered product. He defined a latent defect as a flaw in the design, or in a component part, or in the manufacturing process, which was not immediately detectable but would result in a failure--often within the warranty period. The principle of HALT was to apply increasing levels of an appropriate stress to pre-production samples to precipitate latent design defects, indicating areas of inadequate robustness. It was essential to monitor the product throughout. Page described how HALT evaluations were performed on the Smart drive train, which was an integrated assembly of motor and electronics weighing over 60kg. Problems were identified in connectors and in the power supply unit, targeted changes were incorporated and not only was the drive train supplier able to deliver reliable systems on schedule, savings were made in lifecycle costs because warranty returns were reduced.In a change to the published agenda, Tom Forsyth from Kyzen stepped in at short notice to talk about technology innovations for cleaning highly dense assemblies. He explained some of the reasons why, in an era of no-clean fluxes, cleaning was coming back on the horizon and why the removal of process residues was becoming increasingly difficult. As density increased and the z-axis of components decreased, residues in narrow gaps under components posed an escalating reliability risk. Bottom-termination components complicated the issue and lead-free soldering made cleaning an even tougher challenge. Forsyth listed and examined the process factors that determined the design and selection of cleaning agents, beginning with soils, which could be classified into three categories: Polar or ionic, non-polar, or non-ionic, and particulate. Formulation of cleaning processes started with a good understanding of the physics and physical chemistry of interactions between materials: Coulomb’s Law, Van der Waal’s forces, Hydrogen Bonding and London Dispersive Forces, and of modelling techniques: The Hildebrand solubility model and the Hansen solubility model, which could help to predict whether one material would dissolve in another and offer a means of matching the cleaning agent to the soil. Many other factors needed to be taken into consideration, such as heat exposure, gap height, material compatibility, and cleaning machine characteristics, and the best-engineered cleaning agents were application-specific.Delivering an important message on behalf of high-end PCB fabricators, Wim Perdu, CTO of ACB in Belgium, gave a down-to-earth presentation drawing attention to the cost consequences of over-specifying PCBs. As a long-established manufacturer of high-reliability high-density PCBs, he questioned the real value of specifying boards to IPC-6011 Class 3 and asked whether customers who called-up this standard appreciated the impact on manufacturing, inspection and testing procedures, consequently either underestimating or not even taking into account the costs involved. Class 3 related to high-reliability products where continued performance or performance on demand was critical, for example life support systems and flight control systems. Certain requirements of Class 3 and Class 3A were excessive and unrealistic, and their scientific relevance in respect of quality and reliability was questionable. Nineteen test coupons were required for a standard rigid PCB to Class 3: Perdu showed photographs of typical production panels where the area occupied by coupons exceeded that occupied by the actual circuit. How would the cost be met, and who would pay? Inspection-related requirements were a real cost driver--very few customers realised how much inspection was required to comply with IPC, and very few suppliers explained to customers how much inspection was required. The commercial psychology was that because the competition did not explain it either, and the supplier did not want to push his customer towards the competition, the end result was that most suppliers did not do inspection to full IPC standards, or did not get paid for it, and a vague situation remained in the market.“Don’t expect guaranteed reliability from requiring an IPC class!” Many customers continued to believe that by imposing an IPC class they had specified a reliability guarantee, and would receive PCBs accordingly. This was not the case, but the routine continued due to lack of understanding. “We have seen many boards with very poor quality, although they were certified to be compliant to IPC Class 3.” And it was common for less-scrupulous PCB manufacturers simply to state that they manufactured “in accordance with” IPC without undertaking all of the testing and inspection requirements. Ordering PCBs to Class 3 required proper communication and a clear understanding between customer and supplier before the order was placed, and in many cases design rules needed some adjustment to avoid manufacturing to specification being excessively difficult or even impossible.Perdu’s advice to customers was to select their PCB suppliers properly--"You can’t do it from a spreadsheet!”--visit and audit them, understand and evaluate their technical capabilities and engineering support to optimise customers’ PCB designs and specifications. “Focus on the process and the way reliability is checked when you select a supplier. The process defines the quality and robustness of a PCB. Checking the final product is just a confirmation.”Indium’s Technical Manager for European Operations, Karthik Vijay, discussed the attributes of solder paste necessary for maximising print and reflow manufacturing windows in a context of ongoing miniaturisation, small components and large panels. He reckoned that 80% of SMT defects could be attributed to print defects, and went on to explain how to establish a process window to achieve good print deposits, maximising paste volume and minimising print-to-print variation, for designs with sub-350 micron stencil apertures, summarising the demands on paste flux chemistry. Effects of separation speed and blade angle became significant as aperture size became smaller. Many factors previously ignored became very important and the old rules-of-thumb needed to be reviewed and re-written. It had previously been the rule that, for small apertures, slower squeegee speeds and higher pressures should be used although this led to premature stencil wear. But for volume production, high speeds, lower pressures, and high separation speeds could be used, with reduced stencil wear and reduced under-stencil cleaning frequency, provided the flux chemistry was optimised. Focusing on paste performance requirements to overcome defects such as head-in-pillow and graping, Vijay explained the nature and function of the main components in a flux, and the difference between an activator and an oxidation barrier: an activator reduced oxide after it had formed, whereas an oxidation barrier prevented it from forming in the first place. To eliminate head-in-pillow defects, a paste needed excellent oxidation barrier characteristics, high transfer efficiency, low slump and high tack. The graping phenomenon was almost always associated with small passive components and eliminating the effect depended on the flux providing an effective oxidation barrier. In every case, the key was to optimise the flux chemistry.Vijay also discussed how the process window for certain designs could be increased by the use of engineered solder pre-forms to fortify solder joints and reduce voiding. In one QFN example he quoted, voiding was reduced from 40 to 20% when engineered pre-forms were used.Having learned much about the significance of flux parameters in high-yield paste printing, delegates had the opportunity to understand the effects of the stencil, with a presentation on the state-of-the-art in stencil technology from Lucian Ripperger of Christian Koenen in Germany. Christian Koenen had many years of experience, they had been laser-cutting stencils since 1994, and the benefit of a large applications centre. As already described in Karthik Vijay’s presentation, probably the biggest challenge to be overcome in stencil printing was to get the paste to release cleanly from the sidewalls of the aperture, and the surface condition of the sidewall was critical. Several methods existed to improve the surface: Christian Koenen had cooperated with the Fraunhofer institute to develop an electropolishing technique, which gave release characteristics similar to those of electroformed nickel stencils, but with the material and precision benefits of laser-cut stainless steel. A recent development was a plasma coating which gave a low-energy surface and reduced the adhesion of solder paste, giving more efficient and consistent volume transfer with a corresponding increase in yield and service life of the stencil. Unlike some nano-coatings currently being offered, the plasma coating did not wear off in use, and there were no health-and-safety issues.Ripperger also discussed applications where three-dimensional stencils, stepped on the underside, offered specific benefits, such as the ability to print down into cavities, then introduced a new concept which had been developed for use in photovoltaic manufacture but had some important potential applications in SMT. M-TeCK had been optimised to meet future requirements, with the ability to produce surfaces with layer thicknesses in the millimetre range.SMART Vice Chairman Graham Naisbitt brought the first day’s programme to a close with some frightening statistics on the increasing incidence of counterfeit components. No manufacturer of electronic products was immune to the problem and the consequential costs to electronics manufacturers of inadvertently purchasing counterfeit components and experiencing lost yield, field failures, product recalls and safety issues, could be enormous. Where did counterfeits come from, “Not all from China…,” and what percentage of board assemblers conducted pre-stock testing? What was the reporting procedure if counterfeits were detected? According to figures quoted by Naisbitt, 56% of original component manufacturers, 65% of distributors and 75% of board assemblers did not know whom to call.Naisbitt described the objectives of the EU FP7 part-funded ChipCheck project, in which SMART Group was a partner, which sought to address the counterfeiting issue by developing a non-destructive testing system that would automatically inspect components in their original packaging. The ChipCheck CD-ROM, which gave an introduction to counterfeit components and inspection, was available as a free-of-charge download from the SMART Group website www.smartgroup.org.