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NPL Webinar: Practical Applications for Nanoelectronics

On the basis of “More than Moore” extrapolation, the International Technology Roadmap for Semiconductors (ITRS) predict that future performance will be limited by current interconnect technologies unless new materials are implemented.

The Nanocarbon Electronic Interconnects project is a collaboration between National Physical Laboratory (NPL) and University of Surrey, aimed at developing characterisation tools for nanointerconnects based on nanocarbon. Researcher Vimal Gopee presented a webinar October 10, 2012 to review the limitations of current technologies and demonstrate how carbon nanotubes can present an alternative to existing materials and satisfy ITRS requirements for conductivity, reduced dielectric permittivity, manufacturability and reliability.

Of the available range of nanocarbon species, carbon nanotubes offer the most viable option. In essence they consist of strips of graphene, a two-dimensional graphitic structure one atom thick, rolled into cylinders. They can be produced in extremely high aspect ratio, with a diameter as little as 1 nanometre and lengths of over 1 millimetre, and are classified as single-wall or multi-wall. Depending on the angle of rolling, a single-wall nanotube can exhibit metallic or semiconducting properties, whereas multi-wall nanotubes are almost always metallic conductors.

They can be synthesised by several routes. The materials evaluated at NPL are produced by chemical vapour deposition from a hydrocarbon feedstock gas such as methane or acetylene on a silicon substrate, which yield carbon nanotubes suitable for CMOS applications.

Compared with metals, carbon nanotubes give efficient electron transport with negligible electromigration and exhibited low resistivity, high thermal conductivity, and high tensile strength. Limitations are high contact resistance and chemical inertness, and the main challenge is achieving good adhesion to solder. Significant improvement in adhesion can be made by activation with oxygen plasma followed by sputtering with gold, palladium, or nickel.

Gopee described a process for interconnect fabrication whereby carbon nanotubes are produced as a vertically aligned array on a silicon substrate, their free ends activated then soldered to copper. The nanotube array is then subsequently detached from the silicon and the activation process repeated on the newly freed ends, which are then soldered to copper. The interconnect formed is predicted to be more compliant to thermal expansion mismatch than a BGA joint. A 4 mm x 4 mm sample requires a tensile stress of 20 newtons to break it, and the failure is within the array and not at the interface with solder.

Work is ongoing to assess contact resistance and thermal conductivity, compared with standard solder-copper joints, and to observe the performance of carbon nanotube interconnects under thermal cycling and fatigue testing conditions.

Other potential areas of application of carbon nanotubes include field effect transistors, field emitters, and flexible electronics.

This NPL webinar, coordinated and moderated by Bob Willis, gave a succinct introduction to the concept of carbon nanotube interconnection and Vimal Gopee is to be congratulated for the clarity of his presentation.