- pcb007 Magazine
Getting to Know Your Designer
In this issue, we examine how fabs work with their design customers, educating them on the critical elements of fabrication needed to be successful, as well as the many tradeoffs involved. How well do you really know your customer? What makes for a closer, more synchronized working relationship?
In this issue, the biggest names in PCB manufacturing share their economic outlook for the upcoming year and beyond. As you will see, they were all bullish on our industry, but there was some apprehension as well. No one wants to get burned by another the supply chain disruption.
- Events||| MENU
- pcb007 Magazine
Estimated reading time: 9 minutes
The European Angle
By Pete Starkey
< Back To Columns
Contact Columnist Form
EIPC Winter Conference: Specialization - Europe's Advantage, Part I
Over 90 delegates from 16 countries attended the 2013 EIPC Winter Conference in Berlin, Germany, to exchange information on market conditions and future innovations in interconnection and packaging. Following two excellent, but sobering, keynote presentations on world market trends, the 17-paper technical programme commenced with a session on new substrates and surface finishes moderated by Paul Waldner.
The first presentation was given by Raymond Gales of Circuit Foil in Luxembourg, who described the latest developments in ultra-flat-profile electrodeposited copper foils. He explained that copper surface roughness had become a significant factor influencing conductor losses in high-speed PCBs, particularly in the 10GHz range and above. The current series of roughness classifications defined in IPC-4562A, and the terms “low-profile” and “very-low-profile,” were not sufficient to define the kind of surface required to minimise signal attenuation, and a new “flat-profile” category was under discussion with maximum 2.5-micron roughness.
New copper foils had been developed that achieved very smooth surfaces, together with ultra-flat treatments that were very dense and uniform, and increased the active surface to provide a secure bond to the proprietary resin systems used for low-loss PCBs. The reduction of the treatment profile gave essential advantages for low-loss resin systems and significantly improved insertion loss and skin effect, opening up new opportunities in the antenna and high-speed sector.
To promote bonding and maintain high peel strength, thin primer-resin coatings were being applied to “almost-no-profile” foils, and the primer had no adverse effect on the improved low loss behaviour. However, when used in multilayer fabrication, it was important to consider the bonding treatment used in-process by the PCB manufacturer, so that the benefits of the flat-profile foil were not negated. Therefore, low-etch oxide replacement chemistries or, ideally, non-etching adhesion promoters were needed.
“And now for something completely different,” said Christian Borgert, explaining how FELA in Germany had changed from being a basic PCB manufacturer into an innovative system provider. He introduced a proprietary technology for making capacitive input systems based on glass, offering enormous scope for innovative design in touch-buttons and touch-screens. The FELAM GLASLINE principle was to fabricate single-sided printed circuit directly on the back of the glass panel, avoiding the performance and reliability limitations associated with attaching pre-fabricated rigid or flexible circuits with adhesives, and offering a durable and hygienic alternative to membrane switches. He showed examples of applications in building automation, medical devices laboratory devices, sanitary technology, white goods, and consumer electronics.
The technique involved bonding copper foil to the glass with a dielectric medium, then etching the circuit directly in the foil. Components could be mounted on the circuit and reflow soldered. The glass could be printed with designs in a range of thermally and UV stable colours before the bonding of the foil and areas could be selectively illuminated. The glass panel could even be used as the resonator in a loudspeaker system. A variant was FELAM MACUSLINE, which used similar principles to fabricate touch terminals on stainless steel.
Dr. Tim Von Werne from Semblant in UK gave an insight into an alternative solderable finish which offered improvements in RF performance and PCB shelf life. The Semblant SPF process used plasma polymerisation to deposit a very thin fluoropolymer film on the surface of the PCB, which offered environmental protection and corrosion resistance but facilitated soldering. The coating process involved no water and energy requirements were minimal. No conflict metals were involved and no hazardous waste was produced. Although generally applied direct to copper, the finish could be used to protect any surface metal: Silver, gold, nickel, aluminium, tin, etc.
A major benefit of SPF when used as a replacement for ENIG and ENEPIG finishes on PCBs for high-speed applications was an improvement in signal integrity by eliminating the skin effect associated with electroless nickel. Particularly good results had been observed when using SPF in combination with immersion silver.
The durability of the finish had been extensively evaluated by corrosion testing, and SPF had been independently demonstrated to significantly improve the corrosion resistance of every metallic surface tested.
Semblant had formed a working partnership with Stevenage Circuits in the UK, who were operating the SPF process commercially and offering it to their customers as an optional alternative finish.
The final paper in the substrates and surface finishes session came from Mustafa Oezkoek from Atotech in Germany, with an inroduction to PallaBond direct palladium with direct gold, described as a revolutionary surface finish driven by the needs of new assembly technologies such as copper wire bonding, which was forecast to grow by over 10% year-on-year as a lower-cost alternative to gold wire-bonding, and chip assembly by thermo-compression.
Nickel was increasingly seen as undesirable technically, in high-frequency and fine line applications, as well as environmentally. Therefore alternatives had been sought for ENIG and ENEPIG finishes. The PallaBond process deposited a thickness of only 100 to 200 nanometres of electroless palladium, with an optional 100 nanometres of immersion gold, compared with a typical overall thickness of 5 to 7 microns for ENEPIG, and offered significant cost savings as well as technical benefits. Direct electroless palladium on copper was suitable for soldering, pure copper wire-bonding and palladium coated wire-bonding. The addition of immersion gold made it suitable for gold wire bonding also.
Further technical benefits were good solder joint strength for lead-free and eutectic solders, good compatibility with PCB materials because of short process times at low temperatures, good bending performance if used on flexible circuits, and suitability for key-press applications. Environmentally, the pure electroless palladium finish involved no toxic chemicals and consumed less water and less power in operation than traditional finishes.
At the conclusion of the first technical session, delegates were invited to tour the impressive laboratory facilities at Atotech’s Berlin Headquarters.
The second conference day commenced with a session on reliability and testing, moderated by Professor Martin Goosey, and his first presenter was Professor Rimantas Ramanauskas from LIOC in Lithuania, one of the leading participants in the FP7 ASPIS project which Professor Goosey was coordinating on behalf of the Institute of Circuit Technology (ICT).
Professor Ramanauskas continued to lead an investigation into the fundamental failure mechanisms in the electroless nickel-immersion gold process that caused the “black pad” effect,and gave an update on his findings.
It had been established that the corrosion properties of nickel-phosphorus alloys were governed mainly by phosphorus content, and that the black pad phenomenon was related to the specific structure of the nickel-phosphorus coating and some peculiarities of the immersion gold process. Inadequate copper surface preparation resulted in deposition of nickel-phosphorus with a nodular morphology and serious structural defects such as pores and cavities, which eventually led to direct contact between the copper substrate and components of the immersion gold solution. Meanwhile, gold layers deposited from solutions contaminated with copper ions appeared to be highly porous, with poor adhesion to the nickel coating. Consequently, such gold deposits did not protect the nickel surface from corrosion and could eventually lead to black pad failure of solder joints.
Based on the results of current work, it was recommended that the operating pH of the electroless nickel bath be maintained below 5.5, with an optimum of 4.8, and that the stabiliser concentration be maintained below 0.01 mmol/l, to achieve a nickel deposit with the desired 10 to 11 wt % phosphorus and a the optimal surface activity for gold deposition. Furthermore, it was important to maintain copper concentration in the immersion gold bath below 3 mg/l.
The interconnection stress test is widely used to determine through-hole reliability, and registers a failure when the resistance of a plated-through hole increases by more than a specified amount. This increase in resistance commonly results from a barrel crack, the extent of which is difficult to determine by conventional microsectioning. Dr. Klaus Ritz, industry specialist from Germany, set out to establish a mathematical formula that could be used as a quantitative measure of the extent of crack propagation. The challenge was to model the plated hole in the form of a resistance cylinder with a conical cut-out, taking into consideration the stress-strain mechanical properties of copper, which had only a very narrow elastic region before plastic deformation occurred.
Although the complexities of Dr. Ritz’s mathematics were beyond the comprehension of some members of the audience, he convincingly demonstrated that his calculated values corresponded accurately with experimental data. It appeared that the resistance increase depended only on the angle at the centre of the circumferential barrel crack, the nominal copper thickness at the entrance to the hole, the hole diameter and the board thickness, but not on the vertical position of the crack. A 10% increase in resistance corresponded to an angle of 70 degrees at the centre. Thermo-mechanical analysis, using the z-expansion of a plated-through hole, could be used to estimate the number of cycles to failure, and this information could contribute to design guidelines for improved reliability.
Yvonne Welz from Atotech in Germany had used interconnection stress testing as a means of assessing the reliability of electroless copper, and shared her practical experiences in the next presentation. Whereas IST was commonly used for measuring the through-hole reliability of relatively heavy electroplated copper, and the barrel crack was the predominant failure mechanism, a specially adapted technique was necessary in order to evaluate electroless copper. Specifically, the coating was very thin, and the failure mechanism at issue was the interconnection defect ICD, also known as post separation, a failure of the interconnection between a plated-through hole and an inner layer pad. Therefore, the test conditions and the coupon layout needed to be carefully chosen.
Three failure modes were possible: Separation between electroless copper and inner-layer copper, separation between electroless copper and electroplated copper, and separation within the electroless copper itself. And failure mechanisms for thermal cycling were different from those for solder shock. To achieve best sensitivity, a test coupon had been designed with 1.0 mm diameter holes and 40 micron electroplating, and the daisy chain was arranged so that only ICDs would be detected and barrel cracks would not interfere with the results.
Fifteen different electroless copper and direct plating processes had been subjected to a controlled programme of IST testing, and Weibull statistical methods used to rank the results. This testing technique was now adopted as a standard procedure in Atotech for evaluating electroless copper reliability.
Dr. Golta Khatibi from the University of Vienna discussed the principles of accelerated mechanical testing and explained how it could be used as an alternative method for qualification of microelectronic devices. Present methods for reliability assessment generally relied on accelerated power and temperature cycling and attempts to shorten time-to-failure could result in damage mechanisms that were not representative of real applications. A cost and time saving alternative was to replace thermally induced strains with equivalent mechanical strains. By using accelerated mechanical fatigue equipment, the test structures could be subjected to single and multi-axial loading at high testing frequencies and lifetime curves obtained. A physics-of-failure approach enabled the rapid detection of weak sites in the devices, and experimental results demonstrated the applicability of the method for qualification of first and second-level interconnects in power semiconductors.
Dr. Khatibi described the main features of the test equipment and showed many examples of failures that had been detected, including aluminium wedge bonds in power devices, ultrasonic welded copper-copper interconnects, thermosonic bonded devices, and copper-aluminium ball bonds. A modification of the equipment enabled the study of fatigue cracking in copper-alumina-copper substrates and PCBs during three point bending. And extensive work had been carried out to observe the mechanical reliability of solder joints and the effects of vibrational fatigue of solder balls in BGA assemblies. Lifetime predictions were possible by a combination of accelerated mechanical testing and finite element analysis.Keep an eye out for next week's Tech Tuesday Newsletter and Part II of Pete Starkey's report on the EIPC Winter Conference.
More Columns from The European AngleCircuitData: A New Open Standard for PCB Fab Data Exchange
I Never Realised It Was So Complicated!
The European Angle: Institute of Circuit Technology 43rd Annual Symposium
Ventec International Group's Martin Cotton Celebrates 50 Years in PCB Design
Reporting on the Institute of Circuit Technology Spring Seminar
EuroTech: Raw Materials Supply Chain—Critical Challenges Facing the PCB Industry
EuroTech: ENIPIG—Next Generation of PCB Surface Finish
EuroTech: Institute of Circuit Technology Northern Seminar 2016, Harrogate