Estimated reading time: 13 minutes

EIPC Summer Conference, Day 1

A small landlocked country in western Europe, bordered by Belgium, France, and Germany, Luxembourg covers an area of less than a thousand square miles and has a population of  little more than half a million. The world's only remaining grand duchy, with the world’s highest gross domestic product per capita, Luxembourg was the location for the 2013 Summer Conference of the European Institute of Printed Circuits.

EIPC Chairman Alun Morgan welcomed an international audience, with delegates from 12 countries, to a two-day event with a carefully chosen programme which included a keynote session, 16 technical papers and a visit to the factory of Circuit Foil. After announcing the launch of EIPC’s freshly designed website, www.eipc.org, and inviting papers for the 2014 ECWC World Conference, www.ecwc13.org, Morgan introduced the Keynote presentation from Phil Plonski of Prismark Partners, who held the rapt attention of the audience with a fascinating discussion exploring the challenges and opportunities presented by new design trends and manufacturing technologies for PCBs.

Plonski commented that the electronics industry was increasingly mature, with relatively anaemic growth trends and a constant demand for cost reduction. But traditional market segmentation disguised an important issue: the division between mature and growth segments. And in reality the growth segment still presented tremendous opportunities for complex, useful, cost-effective electronics, the principal drivers being high-functional portable devices, computing and communications infrastructure and the increasing functionality of automotive electronics. Virtually everything else fell into the classification of “mature technology,” which was where the opportunities had been in the past but where costs were now rapidly reducing. Current technology areas of interesting activity in PCB fabrication were flexibles, package substrates and microvia HDI.

“We take things apart!” Plonski declared, as he showed a series of tear-down cross-sections of current high-end mobile devices, revealing a spectacular array of features. “You find a lot of interesting technology when you micro-section things!” One of his examples was the Samsung EXYNOS 5410 system-on-a-chip processor, used in the Galaxy S4 smartphone, with an octa-core CPU package using 28 nm HKMG semiconductor technology, and a 2GB LPDDR3 memory package sat on top with flip-chip interconnection. The processor substrate was 2-2-2 microvia construction, 340 microns thick, with 25 micron lines and spaces and 75 micron vias. The whole lot was contained within a package 14.6 mm square and 1.1mm thick, and interconnected to the PCB through 1100 balls at 0.4mm pitch. “It’s always exciting to see how the design community are packing more and more into the z-axis!”

In RF modules the trends were towards size reduction and the integration of multiple functions on the same die. Leading-edge RF module substrate technology was typically 1-2-1 microvia, 700 microns thick, with 70-80 micron lines and spaces and 60 micron vias.

There was increasing convergence of PCB assembly and semiconductor packaging techniques. The desire for true 3-dimensional integration was driving the development of embedded component technologies, and advanced PCB fabrication, assembly and test processes were being exploited to deliver integrated modular functionality. Many of the individual steps were quite mature technologies, early applications were already in production and there were many enabling opportunities in prospect.

Plonski switched his focus to flexibles. Dismantling an iPad 3 had revealed 16 separate flexible and flex-rigid circuits. For example, the display-driver board was 4-layer polyimide flex with 6-layer HDI. There was plenty of evidence of the trend for flexibles fabricators to deliver pre-assembled modules, and also for modules to be capable of utilisation in multiple and diverse applications. “Think modular” was the message.

Turning his attention to the roadmap for flip-chip and CSP packaging, Plonski observed that the trend was to finer line rather than higher layer-count. Substrates with line widths of 20 microns or less and via diameters of 50 microns or less were already available in volume, and he had seen examples of 5 micron line and space full-additive from Japan. “Think small – this is not semiconductor technology, this is upcoming PCB technology!” he declared and showed a series of illustrations of imaginative design in medical and automotive applications. In many instances, the base technologies already existed, as did modules that could be integrated into functional devices at relatively low cost and high volume as a result of creative thinking.

His closing words were “There’s a whole lot of stuff going on that’s going to drive this industry forward….”                                                                                                                                                                                                                                     The second presentation in the keynote session came from Gordon Biezeveld, Business Manager with UL and based in the Netherlands. Quoting Henry Ford: “Obstacles are those frightful things you see when you take your eyes off the goal,” he set out to clarify the myths and mysteries surrounding the likely qualification changes associated with emerging requirements for FR-4 laminates.

Stressing that the definition of “safety” was constantly evolving, he explained that complex issues of the present had replaced concerns of the past and that the safety landscape of tomorrow was yet to be defined.  Looking specifically at FR-4 laminates, the traditional material based on brominated epoxy resin had evolved in response to demands for improved thermal reliability and electrical performance, as well as international environmental directives, to a point where traditional and modified materials were no longer comparable from a testing point of view, and it was clear that some revised classifications were needed.

There had been real problems in getting industry bodies and standards authorities to agree on exact definitions. The 2011 JTPIA/JPCA proposal to classify all laminates with a 130°C relative thermal index, regardless of chemical composition, as FR-4 did not reach consensus, neither did the 2012 UL proposal to categorise FR-4 into groups based on chemistry and performance. But there had been agreement on the 2013 IPC proposal to classify FR4 into two groups based on flame retardant system, resulting in two new UL/ANSI designations: FR-4.0 for brominated and FR-4.1 for halogen-free materials.

What was the impact of this agreement on laminate manufacturers? In essence, traditional brominated FR-4s changed their designation to FR-4.0 and no additional testing was needed, although file and listing cards would be updated to reflect the new nomenclature. But non-halogen materials, designated FR4.1, would require testing for halogen content according to the new paragraph 8.2 in UL 746E. Sample requirements were to be sent to UL by July 2013, and samples submitted for review by February 2014. An issue still to be resolved was that laminate manufacturers would be forced to revise all their technical data sheets and brochures for FR-4 materials.

Solder resist manufacturers would not need to do additional testing on recognised FR4 laminates, but this would be limited to FR4.0 and new work requests would be required to follow the published UL 746E standard, with testing required for each ANSI requested.

Printed circuit manufacturers would not need new type designation or additional testing for their recognised PCBs on FR-4 material, although file updates would be required after completion of laminate and solder resist file review. As for new work requests for PCBs using FR4.0 and FR4.1, the CCIL/MCIL and coatings programmes were OK and applied to the majority of FR-4.0 materials, although some testing would be required for FR-4.1. There were no CCIL/MCIL or coatings programmes in place for FR-4 materials with blended resins. Full testing, including delamination and flammability would be necessary and a new type-designation was required.

Biezeveld acknowledged that end-product users accustomed to ordering FR4-based products would have a hard time understanding the changes, although he invited people to continue to have an open dialogue with UL and to give active input.

Session 1 of the technical programme was moderated by Jean-Claude Roth, Technical Manager at CCI Eurolam in France, whose first speaker was IPC Vice President of International Relations David Bergman, talking about standards and how they affect business. Reminding delegates that their customers were central to their businesses, Bergman explained that standards were a medium for communication. They helped to deliver products faster by not having to specify basic requirements for form, fit and function. Additionally, having standards reduced overall costs through use of a common understanding between users and suppliers, and increased the reproducibility of products and services.

Standards development was a major function of IPC, and Bergman described how the standardisation process worked. The Technical Activities Executive Committee, chaired by Doug Pauls, was the governing body for all standards development work within IPC and was composed of senior technical people from within the electronics manufacturing industry. Standards were developed through committee structures operating at national and international level. Bergman listed 22 separate committees, explaining that there were over 260 subcommittees and task groups, supported by a network of over 10,000 volunteers. The development of a consensus standard followed a logical process, of which the major steps were project initiation notification, project acceptance, working draft development, final draft for industry review, proposed standard for ballot, negative comment resolution and publication, with a typical timeline of up to 36 months start to finish. Participating companies were largely defence and aerospace related.

The most popular standards revolved around printed circuit board assembly, fabrication and design. The top five sellers all had certification programmes associated with them, and the uptake of certification programmes was at record levels. Bergman demonstrated the relevance and applicability of IPC standards and joint-industry standards at just about every stage of the printed circuit design, fabrication, assembly and test process. There were over 300 active standards in the IPC collection, and these were available in multiple languages – for example, standards had been requested in 15 different languages from Europe.

From the business of standards to the technology of filling small holes – Dr Maria Nikolova, Senior Research Fellow with MacDermid in the USA, described an improved copper plating process for filling microvias and through-hole vias.

Driven by demands for better performance, miniaturisation and price reduction of sequential build-up microvia high-density interconnect in portable electronics, techniques of via filling by copper electroplating had become popular, and several proprietary processes were available. But during the deposition of metal in the vias, a substantial thickness tended to be built up on the surface and this limited the ultimate fine-ness of conductor that could be etched. The objective was to formulate an electrolyte that would enable the efficient and reliable filling of blind holes whilst minimising surface deposition.

Dr Nikolova explained the function of the inorganic constituents of an acid copper plating electrolyte: copper metal, sulphuric acid and chloride, and then described how the organic wetter, brightener and leveller additives modified the structure and distribution of the deposited metal. MacDermid’s new formulation enabled shorter cycle times and faster filling than earlier chemistries, and gave significantly lower surface thickness. In the example illustrated, vias 100 microns diameter and 75 microns deep were filled in 40 minutes, with 9 microns at the surface, compared with typically 50 minutes and 14 microns from an established formulation.

Higher concentrations of copper sulphate had been observed to have a positive effect on hole filling, particularly at larger via diameters, whereas sulphuric acid and chloride concentrations had insignificant effect. Of the organic additives, leveller had the most significant effect, as might be expected, whereas beyond a certain concentration brightener had no effect and neither did wetter over a wide concentration range. Bath agitation was also a factor, and high flow rates contributed to dimple formation. All of the via sizes plated exhibited excellent thermal integrity under solder shock conditions. The deposits were bright and levelled, with a fine equiaxial grain structure. The development work had been extended to study the filling of photo-defined bumps and pillars for IC substrates and the filling of through-vias for 3-dimensional chip-stacking applications, with encouraging results.

Spirit Circuits’ Technical Sales Manager Les Round has become a well-known spokesman on the technology and applications of insulated metal substrates. He described a new-generation material developed by Cambridge Nanotherm, where a nanocrystalline dielectric layer of aluminium oxide was formed in-situ on an aluminium base by an electrochemical deposition process. The dielectric was available in thicknesses of 10, 20 and 30 microns, with a thermal conductivity of 7W/mK., The material could be used in applications where extremely low thermal impedance was demanded. Indeed its thermal impedance was less than half of that of the currently best available conventional IMS materials. Copper for circuit fabrication was either press-bonded to the dielectric as a resin-coated foil with 4-micron adhesive or, in a premium version of the material, deposited directly on the dielectric by an electroless plating process. These substrates were competitive in chip-on-board and chip-on-heatsink applications, and offered an alternative to alumina and aluminium nitride tiles.

Round described a practical comparison test conducted in front of a live audience at a recent LED workshop, where a series of “star” PCBs on different IMS substrates were assembled with Cree XM-L high-performance LEDs and thermocouples for temperature monitoring. With the devices powered-up at 1000mA and 3000mA, those based on Nanotherm showed remarkably lower junction temperatures than those based on standard IMS substrates.

Final presentation of Session 1 came from Alfred Kaiserman, AOI and AOR Products Manager with Orbotech in Belgium, who described how users could make best use of the capability and functionality of their automated optical inspection and automated optical repair facilities without additional investment. For example, using an AOI system for checking for presence and position of holes, or detecting annular ring violations by intelligent drill rest-ring reporting. Even if the ring could not be clearly seen, its geometry was precisely calculated and violations were reported only if they contravened defined criteria, rather than be flagged as false alarms. Inclusions in base materials, which might not be detected in a conventional binary image, could be distinguished and reported by the latest image analysis algorithms, and the principle could be applied to the detection of copper shorts under solder mask, or contamination and discolouration of solder pads.

Thick copper had traditionally presented inspection problems to AOI systems, a specific example being the combination of 80 micron copper and white ceramic substrate used in automotive LED lighting. Enhanced-angle illumination and polarised light enabled effective image capture of the etched edges of thick copper tracks, in conjunction with advanced software to analyse the resulting data. Additionally, modern AOI systems could be used for the detection of laser drill defects, and for flex-rigid inspection.

An innovative application of automated optical repair systems was the repair of shorts covered by solder mask. A small window was opened in the solder mask to allow access for the short to be laser-ablated away, and the repair could then be spotted-in with solder mask.

It has become customary in recent years for EIPC conferences to include a visit to a manufacturing plant, and the Luxembourg event gave delegates the opportunity to observe the manufacturing process for copper foil at the factory of Circuit Foil Luxembourg SARL, a bus ride away in Wiltz.

Circuit Foil Customer Care and Group Quality Director Raymond Gales gave an introduction and overview of the operation, which each month converts 850 tons of copper into 3.5 million square metres of foil. In a highly automated process, copper metal is first dissolved in sulphuric acid, and the filtered and purified electrolyte is fed to a series of continuous plating machines. In each plating machine, the cathode is a large-diameter stainless steel cylinder, half-immersed in the electrolyte and continuously rotating at low speed. Copper is electrodeposited at high current density and the deposit is peeled off as a roll of continuous foil. The roll is later transferred to another continuous plating line for the bonding treatment to be applied, then trimmed to width and stored ready to be cut to sheets according to customer requirement. The product range includes standard HTE foils from 12 to 210 microns and a series of special-purpose foils: ultra-flat profile, ultra-thin and resin coated.

Delegates enjoyed a comprehensive guided tour of the plant followed by an evening reception, which brought the proceedings of the first day to a convivial conclusion.

I am grateful to Alun Morgan and Michael Weinhold for allowing me to use their photographs.