**Estimated reading time: 6 minutes**

# Maxed Out: Using Transistors to Build Logic Functions - The Finale!

Archived column from: Clive "Max" Maxfield

In Part 8 of this series we discussed how to construct a CMOS implementation of a 2-input NAND gate using two NMOS and two PMOS transistors (Figure 1). Observe that we could create a three-input version by adding a third PMOS transistor in parallel with transistors T1 and T2 and a third NMOS transistor in series with transistors T3 and T4.

**Figure 1. CMOS implementation of a two-input NAND gate.**

As you will recall, with regard to the "odd man out" case, if inputs 'a' and 'b' are both logic 1, then PMOS transistors T1 and T2 will both be turned OFF, NMOS transistors T3 and T4 will both be turned ON, and output 'y' will be connected to logic 0 via transistors T3 and T4. For any other combination of inputs, transistor T1 and/or T2 will be turned ON, transistor T3 and/or T4 will be turned OFF, and output 'y' will be connected to logic 1 via transistor T1 and/or T2.

Now, it's easy to get confused when you first see something like this. Another way of looking at things is to visualize the transistors as being mechanical switches that we open and close by hand as illustrated in Figure 2 (observe that this figure reflects the case of logic 1 values being presented to both inputs).

**Figure 2. Visualizing our two-input NAND as switches.**

In this case, a logic 0 associated with switch S1 or S2 will cause us to physically close (activate) that switch, while a logic 1 associated with either of these switches will cause us to physically open (deactivate) that switch. By comparison, a logic 0 associated with switch S3 or S4 will cause us to physically open (deactivate) that switch, while a logic 1 associated with either of these switches will cause us to physically close (activate) that switch.

**CMOS implementation of a NOR Gate**

Now, in my last article I asked you to ponder how to implement a two-input NOR gate. In fact, this is topologically the inverse of the NAND as illustrated in Figure 3.

**Figure 3. CMOS implementation of a 2-input NOR gate.**

As usual, let's start with the "odd man out" case, which is both inputs being logic 0. If inputs 'a' and 'b' are both logic 0, then PMOS transistors T1 and T2 will both be turned ON, NMOS transistors T3 and T4 will both be turned OFF, and output 'y' will be connected to logic 1 via transistors T1 and T2. For any other combination of inputs, transistor T1 and/or T2 will be turned OFF, transistor T3 and/or T4 will be turned ON, and output 'y' will be connected to logic 0 via transistor T3 and/or T4.

So now we have three exercises for you to perform: (1) draw a switch diagram representation of this gate (similar in concept to Figure 2) and prove that the gate fulfills the requirements of its truth table, (2) modify this gate to have three inputs, and (3) create a non-inverting OR version of your 3-input gate.

**Why use CMOS?**

Next, let's discuss something that relatively few folks really understand (apart from electronic design engineers, of course). Consider an NMOS implementation of a NOT gate compared to a CMOS realization as illustrated in Figure 4.

**Figure 4. NMOS vs. CMOS implementations of NOT gate.**

So, the question would be: "Why do we predominantly use CMOS implementations as opposed to say NMOS implementations?" I mean, as we see in Figure 4, the CMOS gate requires two transistors, while the NMOS equivalent required only a single transistor and a resistor.

Well, I'm glad you asked. First of all, you may think that a resistor is smaller than a transistor. Boing! In fact, if we were to make the NMOS version of the gate on a silicon chip, we would actually fabricate the resistor as a transistor that was permanently ON (we'd just construct it in such a way that even when it was ON it had a relatively high resistance).

Next, consider what happens if you connect a bunch of the NMOS versions of these gates one after the other as illustrated in Figure 5 (we're showing only five inverters here, but imagine there's a lot more, say 100).

**Figure 5. Stringing a bunch of NMOS inverters together.**

Suppose we start off by applying a logic 0 to input 'a'. This turns transistor T1 OFF (which is just like removing it from the circuit and leaving a gap in the wire), so wire 'w1' is pulled up to a logic 1 by resistor R1.

Remember that, as we've discussed in previous articles, the gate (control) inputs to all of these transistors are formed from small conducting plates that are separated from the transistor itself by a thin insulating (oxide) layer. This means that the gate input is like a really small capacitor. Following the small pulse of current on wire 'w1' required to charge the gate on transistor T2, no more current will flow through resistor R1 (actually, this isn't 100% true, because there will be a tiny amount of leakage, but let's say that it is for the moment).

OK, so now we have a logic 1 on the gate to transistor T2. This turns transistor T2 ON, which is like closing a switch. So wire 'w2' is now connected to logic 0 via transistor T2.

And so it goes down the line, with alternate transistors being turned OFF or ON. The point is that any transistors that are ON (half of all our transistors) result in current flowing through their associated resistors, which equates to power being consumed. Now, the resistors will be a relatively high value, so the power being consumed by a single gate will be very small ... but when you have a chip containing hundreds of thousands or millions of transistors, the power consumption becomes significant and the chip starts to become uncomfortable hot.

Now consider an equivalent chain of CMOS inverters. Once the input has switched and the effect has rippled through the chain, each inverter ends up with one transistor ON, the other transistor OFF, and no power being consumed (this explanation is a bit of a simplification, but it will serve our needs here).

**Coming Next Time...**

Hmmm, what shall we talk about next time? Well, if you have topics you'd like me to cover (like what's the difference between DRAM, SRAM, SDRAM, etc.), then please feel free to email me at max@techbites.com; otherwise I will be more than happy to waffle on about whatever topic takes my fancy at that time. Until next time, have a good one!

**Acknowledgements**This article was abstracted from Bebop to the Boolean Boogie (*An Unconventional Guide to Electronics*) with the kind permission of the publisher.

**About the author**

Clive "Max" Maxfield is president of TechBites Interactive, a marketing consultancy firm specializing in high technology. Max is the author and co-author of a number of books, including Bebop to the Boolean Boogie (*An Unconventional Guide to Electronics*), The Design Warrior's Guide to FPGAs (*Devices, Tools, and Flows*), How Computers Do Math featuring the pedagogical and phantasmagorical virtual DIY Calculator.

In addition to being a hero, trendsetter, and leader of fashion, Max is widely regarded as being an expert in all aspects of computing and electronics (at least by his mother). Max was once referred to as "an industry notable" and a "semiconductor design expert" by someone famous who wasn't prompted, coerced, or remunerated in any way. Max can be contacted at max@techbites.com.

### More Columns from Various Archived Columns

Slash Sheet Chaos: Is What You See, What You Get?Moisture in Materials: Avoiding Process Gremlins

Material Witness: Beat the Heat--A Non-Math Intro to Thermal Properties

Material Witness: Considerations in Using TC Materials for PWBs

Material Witness: Are Your Materials Up to the Challenge?

Material Witness: Thermal Oxidation of Materials, Part I

Material Witness: Thermal Oxidation of Materials, Part II

Material Witness: R.I.P. Speedboard C